Product
0
SN74AHC139-Q1
  • SN74AHC139-Q1
  • SN74AHC139-Q1
  • SN74AHC139-Q1

SN74AHC139-Q1

ACTIVE

Automotive dual 2-line to 4-line demultiplexer and decoder

Texas Instruments SN74AHC139-Q1 Product Info

1 April 2026 0

Parameters

Technology family

AHC

Number of channels

2

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Supply current (max) (µA)

40

Package

TSSOP (PW)-16-32 mm² 5 x 6.4

Features

  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package
  • Operating range 2V to 5.5V VCC
  • Low delay, 10.5ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package
  • Operating range 2V to 5.5V VCC
  • Low delay, 10.5ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17

Description

The SN74AHC139-Q1 contains two 2-line to 4-line decoders/demultiplexers. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The SN74AHC139-Q1 contains two 2-line to 4-line decoders/demultiplexers. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

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