Product
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SN74AC164-Q1
  • SN74AC164-Q1
  • SN74AC164-Q1
  • SN74AC164-Q1
  • SN74AC164-Q1
  • SN74AC164-Q1

SN74AC164-Q1

ACTIVE

Automotive, 1.5V-to-6V, eight bit serial-in parallel-out shift register

Texas Instruments SN74AC164-Q1 Product Info

1 April 2026 4

Parameters

Configuration

Serial-in

Bits (#)

8

Technology family

AC

Supply voltage (min) (V)

1.5

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (MHz)

100

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

20

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Package

TSSOP (PW)-14-32 mm² 5 x 6.4

Features

  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package
  • Wide operating range of 1.5V to 6V
  • Inputs accept voltages up to 6V
  • Continuous ±24mA output drive at 5V
  • Supports up to ±75mA output drive at 5Vin short bursts
  • Drives 50Ω transmission lines
  • Maximum tpd of 12.5ns at 5V, 50pF load
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package
  • Wide operating range of 1.5V to 6V
  • Inputs accept voltages up to 6V
  • Continuous ±24mA output drive at 5V
  • Supports up to ±75mA output drive at 5Vin short bursts
  • Drives 50Ω transmission lines
  • Maximum tpd of 12.5ns at 5V, 50pF load

Description

The SN74AC164-Q1 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

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