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LMK61E0M
  • LMK61E0M
  • LMK61E0M

LMK61E0M

ACTIVE

LVCMOS ultra-low jitter programmable oscillator with internal EEPROM

Texas Instruments LMK61E0M Product Info

1 April 2026 4

Parameters

Output type

LVCMOS

Output frequency (MHz)

200

Stability (ppm)

25

Supply voltage (V)

3.3

Operating temperature range (°C)

-40 to 85

Jitter (ps)

0.5

Package

QFM (SIA)-8-12.25 mm² 3.5 x 3.5

Features

  • Ultra-Low Noise, High Performance
    • Jitter: 500-fs RMS Typical fOUT > 50 MHz on LMK61E0M
  • LMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHz
  • Total Frequency Tolerance of ±25 ppm
  • System Level Features
    • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
    • Internal EEPROM: User Configurable Start-Up Settings
  • Other Features
    • Device Control: Fast Mode I2C up to 1000 kHz
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 8-Pin Package
  • Default Frequency: 70.656 MHz
  • Ultra-Low Noise, High Performance
    • Jitter: 500-fs RMS Typical fOUT > 50 MHz on LMK61E0M
  • LMK61E0M Supports 3.3-V LVCMOS Output up to 200 MHz
  • Total Frequency Tolerance of ±25 ppm
  • System Level Features
    • Glitch-Less Frequency Margining: Up to ±1000 ppm From Nominal
    • Internal EEPROM: User Configurable Start-Up Settings
  • Other Features
    • Device Control: Fast Mode I2C up to 1000 kHz
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 8-Pin Package
  • Default Frequency: 70.656 MHz

Description

The LMK61E0 family of ultra-low jitter PLLatinumTM programmable oscillators use fractional-N frequency synthesizers with integrated VCOs to generate commonly used reference clocks. The LMK61E0M supports 3.3-V LVCMOS outputs. The device features self start-up from on-chip EEPROM to generate a factory programmed default output frequency, or the device registers and EEPROM settings are fully programmable in-system through I2C serial interface. The device provides fine and coarse frequency margining control through I2C serial interface, making it a digitally-controlled oscillator (DCXO).

The PLL feedback divider can be updated to adjust the output frequency without spikes or glitches in steps of <1ppb using a PFD of 12.5 MHz (R divider=4, doubler disabled) for compatibility with xDSL requirements, or in steps of <5.2 ppb using a PFD of 100 MHz (R divider=1, doubler enabled) for compatibility with broadcast video requirements. The frequency margining features also facilitate system design verification tests (DVT), such as standards compliance and system timing margin testing.

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