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LMK5C33414A
  • LMK5C33414A

LMK5C33414A

ACTIVE

Three DPLL, three APLL, four-input and 14-output network synchronizer with JESD204B/C and BAW VCO

Texas Instruments LMK5C33414A Product Info

1 April 2026 1

Parameters

Function

Clock network synchronizer

Number of outputs

14

Output type

CML, LVCMOS, LVDS, LVPECL

RMS jitter (fs)

47

Features

JESD204B

Output frequency (min) (MHz)

0.000000000001

Output frequency (max) (MHz)

1250

Input type

HCSL, LVCMOS, LVDS, LVPECL, XTAL

Supply voltage (min) (V)

3.135

Supply voltage (max) (V)

3.465

Operating temperature range (°C)

-40 to 105

Number of input channels

4

Package

VQFN (RGC)-64-81 mm² 9 x 9

Features

  • Ultra-low jitter BAW VCO based Wireless clocks
    • 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
    • 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
  • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
    • Programmable DPLL loop bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • Four differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital holdover and hitless switching
  • 14 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
    • Up to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C, 3-wire SPI, or 4-wire SPI
  • –40°C to 85°C operating temperature
  • Ultra-low jitter BAW VCO based Wireless clocks
    • 40fs typical/ 57fs maximum RMS jitter at 491.52MHz
    • 50fs typical/ 62fs maximum RMS jitter at 245.76MHz
  • Three high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)
    • Programmable DPLL loop bandwidth from 1mHz to 4kHz
    • < 1ppt DCO frequency adjustment step size
  • Four differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital holdover and hitless switching
  • 14 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formats
    • Up to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N
    • 1Hz (1PPS) to 1250MHz output frequency with programmable swing and common mode
    • PCIe Gen 1 to 6 compliant
  • I2C, 3-wire SPI, or 4-wire SPI
  • –40°C to 85°C operating temperature

Description

The LMK5C33414A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

The LMK5C33414A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications.

The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use.

APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain.

Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs.

The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.

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