- FMCW Transceiver
- Integrated PLL, transmitter, receiver, baseband and ADC
- 57 - 64GHz coverage with 7GHz continuous bandwidth
- 4 receive channels and 3 to 4 transmit channels (IWRL6843 with 3 channels and IWRL6844 with 4 channels)
- 12.5dBm typical output power per TX
- 12.5dB typical noise figure
- -90.5dBc/Hz typical phase noise at 1MHz
- FMCW operation
- 10MHz IF bandwidth, real-only Rx channels
- Ultra-accurate chirp engine based on fractional-N PLL
- Per transmitter binary phase shifter
- Processing elements
- Arm R5F core with double precision FPU (200MHz)
- Hardware Accelerator (HWA 1.2) for FFT, log magnitude, and CFAR operations (200MHz)
- C66x DSP (450MHz) for processing Radar data
- Supports multiple low-power modes
- Idle mode and deep sleep mode
- Power management
- 1.8V and 3.3V IO support
- Built-in LDO network for enhanced PSRR
- Two power rails for 1.8V IO mode, Three power rails for 3.3V IO mode
- FCCSP package having 17 x 17 BGA grid, 207 BGA balls; Package size: 9.1mm x 9.1mm
- Built-in calibration and self-test
- Built-in Firmware (ROM)
- Self-Contained on chip calibration system
- Host Interfaces
- 3 x UART
- 2 x CAN-FD
- 2 x SPI
- LVDS for data transfer of raw ADC sample capture
- Other interfaces available to user application
- QSPI
- I2C
- JTAG
- 8 x GPIOs
- PWM Interface
- 4 x GPADCs
- Device security (on Secure device variants)
- Programmable embedded hardware security module (HSM)
- Secure authenticated and encrypted boot support
- Customer programmable root keys, symmetric keys (256 bit), asymmetric keys (up to RSA-4K or ECC-512) with key revocation capability
- Cryptographic hardware accelerators: PKA with ECC/RSA, AES (up to 256 bit), SHA (up to 512 bit), TRNG/DRBG and SM2, SM3, SM4(Chinese Crypto Algorithms)
- Product Cybersecurity Compliance
- Developed for cybersecurity-relevant applications
- Documentation will be available to aid cybersecurity system design
- Internal memory
- Functional Safety-Compliant Targeted
- Developed for Functional Safety Applications
- Documentation will be available to aid functional safety system design
- Hardware integrity up to SIL 2 targeted as per IEC61508 standard
- Clock source
- 40.0MHz crystal for primary clock
- Supports externally driven clock (Square/Sine) at 40.0MHz
- 32kHz internal oscillator for low power operations
- Operating temperature range
- Junction Temperature Range: –40°C to 105°C
- FMCW Transceiver
- Integrated PLL, transmitter, receiver, baseband and ADC
- 57 - 64GHz coverage with 7GHz continuous bandwidth
- 4 receive channels and 3 to 4 transmit channels (IWRL6843 with 3 channels and IWRL6844 with 4 channels)
- 12.5dBm typical output power per TX
- 12.5dB typical noise figure
- -90.5dBc/Hz typical phase noise at 1MHz
- FMCW operation
- 10MHz IF bandwidth, real-only Rx channels
- Ultra-accurate chirp engine based on fractional-N PLL
- Per transmitter binary phase shifter
- Processing elements
- Arm R5F core with double precision FPU (200MHz)
- Hardware Accelerator (HWA 1.2) for FFT, log magnitude, and CFAR operations (200MHz)
- C66x DSP (450MHz) for processing Radar data
- Supports multiple low-power modes
- Idle mode and deep sleep mode
- Power management
- 1.8V and 3.3V IO support
- Built-in LDO network for enhanced PSRR
- Two power rails for 1.8V IO mode, Three power rails for 3.3V IO mode
- FCCSP package having 17 x 17 BGA grid, 207 BGA balls; Package size: 9.1mm x 9.1mm
- Built-in calibration and self-test
- Built-in Firmware (ROM)
- Self-Contained on chip calibration system
- Host Interfaces
- 3 x UART
- 2 x CAN-FD
- 2 x SPI
- LVDS for data transfer of raw ADC sample capture
- Other interfaces available to user application
- QSPI
- I2C
- JTAG
- 8 x GPIOs
- PWM Interface
- 4 x GPADCs
- Device security (on Secure device variants)
- Programmable embedded hardware security module (HSM)
- Secure authenticated and encrypted boot support
- Customer programmable root keys, symmetric keys (256 bit), asymmetric keys (up to RSA-4K or ECC-512) with key revocation capability
- Cryptographic hardware accelerators: PKA with ECC/RSA, AES (up to 256 bit), SHA (up to 512 bit), TRNG/DRBG and SM2, SM3, SM4(Chinese Crypto Algorithms)
- Product Cybersecurity Compliance
- Developed for cybersecurity-relevant applications
- Documentation will be available to aid cybersecurity system design
- Internal memory
- Functional Safety-Compliant Targeted
- Developed for Functional Safety Applications
- Documentation will be available to aid functional safety system design
- Hardware integrity up to SIL 2 targeted as per IEC61508 standard
- Clock source
- 40.0MHz crystal for primary clock
- Supports externally driven clock (Square/Sine) at 40.0MHz
- 32kHz internal oscillator for low power operations
- Operating temperature range
- Junction Temperature Range: –40°C to 105°C