0
ACTIVE
Function |
Receiver |
Protocols |
LVDS |
Number of transmitters |
0 |
Number of receivers |
4 |
Supply voltage (V) |
5 |
Signaling rate (Mbps) |
155.5 |
Input signal |
LVDS |
Output signal |
TTL |
Rating |
Catalog |
Operating temperature range (°C) |
-40 to 85 |
SOIC (D)-16-59.4 mm² 9.9 x 6
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The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device supports data rates in excess of 155.5 Mbps (77.7 MHz) and uses Low Voltage Differential Signaling (LVDS) technology.
The DS90C032B accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032B provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C032B and companion line driver (DS90C031B) provide a new alternative to high power pseudo-ECL devices for high-speed point-to-point interface applications.
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