Product
0
DAC38RF85
  • DAC38RF85
  • DAC38RF85
  • DAC38RF85
  • DAC38RF85
  • DAC38RF85
  • DAC38RF85
  • DAC38RF85
  • DAC38RF85
  • DAC38RF85

DAC38RF85

ACTIVE

14-Bit, 9-GSPS, 6x-24x Interpolating, 6 & 9 GHz PLL Digital-to-Analog Converter (DAC)

Texas Instruments DAC38RF85 Product Info

1 April 2026 0

Parameters

Resolution (Bits)

14

Number of DAC channels

1

Interface type

JESD204B

Sample/update rate (Msps)

9000

Features

Ultra High Speed

Rating

Catalog

Interpolation

10x, 12x, 16x, 18x, 20x, 24x, 6x, 8x

Power consumption (typ) (mW)

2195

SFDR (dB)

97

Architecture

Current Source

Operating temperature range (°C)

-40 to 85

Reference type

Ext, Int

Package

FCCSP (AAV)-144-100 mm² 10 x 10

Features

  • 14-bit resolution
  • Maximum DAC sample rate: 9 GSPS
  • Key Specifications:
    • RF full-scale output power at 2.1 GHz:
      • DAC38RF80/90/84: 0 dBm
      • DAC38RF83/93/85: 3 dBm (with 2:1 balun)
    • Spectral performance(on-chip PLL, DIFF):
      • fDAC = 5898.24 MSPS, fOUT = 2.14 GHz
        • WCDMA ACLR: 75 dBc
        • WCDMA alt-ACLR: 77 dBc
      • fDAC = 8847.36 MSPS, fOUT = 3.7 GHz
        • 20 MHz LTE ACLR: 63 dBc
      • fDAC = 9 GSPS, fOUT = 1.8 GHz
        • IMD3 = 70 dBc (–6 dBFS, 10-MHz tone spacing)
        • NSD = –157 dBc/Hz
  • Dual-band digital up-converter per DAC
    • 6, 8, 10, 12, 16, 18, 20 or 24x interpolation
    • 4 Independent NCOs with 48-bit resolution
  • JESD204B Interface, subclass 1
    • Support for multichip synchronization
    • Maximum lane rate: 12.5 Gbps
  • Single-ended output with integrated balun (DAC38RF80/90/84) covering 700 MHz to 3800 MHz
  • Internal PLL and VCO with bypass
    • fC(VCO) = 5.9 or 8.9 GHz
  • Power dissipation: 1.4 to 2.2 W/ch
  • Power supplies: –1.8 V, 1 V, 1.8 V
  • Package: 10 x 10 mm BGA, 0.8 mm pitch, 144-balls
  • 14-bit resolution
  • Maximum DAC sample rate: 9 GSPS
  • Key Specifications:
    • RF full-scale output power at 2.1 GHz:
      • DAC38RF80/90/84: 0 dBm
      • DAC38RF83/93/85: 3 dBm (with 2:1 balun)
    • Spectral performance(on-chip PLL, DIFF):
      • fDAC = 5898.24 MSPS, fOUT = 2.14 GHz
        • WCDMA ACLR: 75 dBc
        • WCDMA alt-ACLR: 77 dBc
      • fDAC = 8847.36 MSPS, fOUT = 3.7 GHz
        • 20 MHz LTE ACLR: 63 dBc
      • fDAC = 9 GSPS, fOUT = 1.8 GHz
        • IMD3 = 70 dBc (–6 dBFS, 10-MHz tone spacing)
        • NSD = –157 dBc/Hz
  • Dual-band digital up-converter per DAC
    • 6, 8, 10, 12, 16, 18, 20 or 24x interpolation
    • 4 Independent NCOs with 48-bit resolution
  • JESD204B Interface, subclass 1
    • Support for multichip synchronization
    • Maximum lane rate: 12.5 Gbps
  • Single-ended output with integrated balun (DAC38RF80/90/84) covering 700 MHz to 3800 MHz
  • Internal PLL and VCO with bypass
    • fC(VCO) = 5.9 or 8.9 GHz
  • Power dissipation: 1.4 to 2.2 W/ch
  • Power supplies: –1.8 V, 1 V, 1.8 V
  • Package: 10 x 10 mm BGA, 0.8 mm pitch, 144-balls

Description

The DAC38RFxx is a family of high-performance, dual/single-channel, 14-bit, 9-GSPS, RF-sampling digital-to-analog converters (DACs) that are capable of synthesizing wideband signals from 0 to 4.5 GHz. A high dynamic range allows the DAC38RFxx family to generate signals for a wide range of applications including 3G/4G signals for wireless base-stations and radar.

The devices feature a low-power JESD204B Interface with up to 8 lanes with a maximum bit rate of 12.5 Gbps allowing an input data rate of 1.25 GSPS complex per channel. The DAC38RFxx provides two digital up-converters per channel, with multiple options for interpolation rates. A digital quadrature modulator with independent, frequency flexible NCOs are available to support multi-band operation. An optional low-jitter PLL/VCO simplifies the DAC sampling clock generation by allowing use of a lower frequency reference clock.

The DAC38RFxx is a family of high-performance, dual/single-channel, 14-bit, 9-GSPS, RF-sampling digital-to-analog converters (DACs) that are capable of synthesizing wideband signals from 0 to 4.5 GHz. A high dynamic range allows the DAC38RFxx family to generate signals for a wide range of applications including 3G/4G signals for wireless base-stations and radar.

The devices feature a low-power JESD204B Interface with up to 8 lanes with a maximum bit rate of 12.5 Gbps allowing an input data rate of 1.25 GSPS complex per channel. The DAC38RFxx provides two digital up-converters per channel, with multiple options for interpolation rates. A digital quadrature modulator with independent, frequency flexible NCOs are available to support multi-band operation. An optional low-jitter PLL/VCO simplifies the DAC sampling clock generation by allowing use of a lower frequency reference clock.

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