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CDCBT1001
  • CDCBT1001
  • CDCBT1001

CDCBT1001

ACTIVE

1.2-V to 1.8-V clock buffer and level translator

Texas Instruments CDCBT1001 Product Info

1 April 2026 4

Parameters

Number of outputs

1

Core supply voltage (V)

1.2

Output supply voltage (V)

1.8

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVCMOS

Input type

LVCMOS

Package

X2SON (DPW)-5-0.64 mm² 0.8 x 0.8

Features

  • Low additive jitter and phase noise:
    • 0.8ps maximum 12kHz to 5MHz additive RMS jitter (fout = 24MHz)
    • –120dBc/Hz maximum phase noise at 1kHz offset (fout = 24MHz)
    • –148dBc/Hz maximum phase noise floor (fout = 24MHz, foffset ≥ 1MHz)
  • 5ns 20% to 80% rise/fall time
  • 10ns propagation delay
  • Low current consumption
  • –40°C to 85°C operating temperature range
  • Flexible output from operational frequency
  • Low additive jitter and phase noise:
    • 0.8ps maximum 12kHz to 5MHz additive RMS jitter (fout = 24MHz)
    • –120dBc/Hz maximum phase noise at 1kHz offset (fout = 24MHz)
    • –148dBc/Hz maximum phase noise floor (fout = 24MHz, foffset ≥ 1MHz)
  • 5ns 20% to 80% rise/fall time
  • 10ns propagation delay
  • Low current consumption
  • –40°C to 85°C operating temperature range
  • Flexible output from operational frequency

Description

The CDCBT1001 is a 1.2V to 3.3V clock buffer and level translator. The VDD_IN pin supply voltage defines the input LVCMOS clock level. The VDD_OUT pin supply voltage defines the output LVCMOS clock level. VDD_IN = 1.2V, 1.8V, 2.5V, or 3.3V ± 10%. VDD_OUT = 1.2V, 1.8V, 2.5V, or 3.3V ± 10%.

The 12kHz to 5MHz additive RMS jitter at 24MHz is less than 0.8ps.

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