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CD74HCT73
  • CD74HCT73
  • CD74HCT73
  • CD74HCT73

CD74HCT73

ACTIVE

High speed CMOS logic dual negative-edge-triggered J-K flip-flops with reset

Texas Instruments CD74HCT73 Product Info

1 April 2026 1

Parameters

Number of channels

2

Technology family

HCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL

Output type

Push-Pull

Clock frequency (MHz)

24

Supply current (max) (µA)

80

IOL (max) (mA)

6

IOH (max) (mA)

-6

Features

Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Package

PDIP (N)-14-181.42 mm² 19.3 x 9.4

Features

  • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
  • Asynchronous reset
  • Complementary outputs
  • Buffered inputs
  • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types
    • 2 V to 6V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5 V to 5.5 V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1 µA at VOL, VOH
  • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
  • Asynchronous reset
  • Complementary outputs
  • Buffered inputs
  • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types
    • 2 V to 6V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5 V to 5.5 V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1 µA at VOL, VOH

Description

CD74HCT73:High speed CMOS logic dual negative-edge-triggered J-K flip-flops with reset.Package:PDIP (N)-14-181.42 mm² 19.3 x 9.4

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