Product
0
ADC3664-SP
  • ADC3664-SP
  • ADC3664-SP
  • ADC3664-SP
  • ADC3664-SP

ADC3664-SP

ACTIVE

Radiation-hardness-assured (RHA), QMLV, 300-krad, 14-bit, dual 125-MSPS ADC

Texas Instruments ADC3664-SP Product Info

1 April 2026 4

Parameters

Sample rate (max) (Msps)

125

Resolution (Bits)

14

Number of input channels

2

Interface type

Serial LVDS

Analog input BW (MHz)

200

Features

Bypass Mode, Decimating Filter, Differential Inputs, Dual Channel, High Dynamic Range, High Performance, Internal Reference, LVDS interface, Low latency, Low power

Rating

Space

Peak-to-peak input voltage range (V)

3.2

Power consumption (typ) (mW)

200

Architecture

SAR

SNR (dB)

78

ENOB (Bits)

12.6

SFDR (dB)

84

Operating temperature range (°C)

-40 to 105

Radiation, TID (typ) (krad)

300

Radiation, SEL (MeV·cm2/mg)

75

Package

CFP (HBP)-64-862.0096 mm² 29.36 x 29.36

Features

  • Screening and radiation performance
    • QMLV screening and reliability assurance
    • Total ionizing dose (TID): 300krad (Si)
    • Single event latch-up (SEL): 75MeV-cm2/mg
  • Ambient temperature range: -55°C to 105°C
  • Dual Channel ADC
  • 14-bit 125MSPS
  • Noise floor: -156.9dBFS/Hz
  • Low power consumption: 100mW/ch
  • Latency: 2 clock cycles
  • Clock rate versus voltage reference:
    • External reference: 1MSPS to 125MSPS
    • Internal reference: 100MSPS to 125MSPS
  • 14-Bit, no missing codes
  • Input bandwidth: 200MHz (-3dB)
  • INL: ±2.6LSB; DNL: ±0.9LSB
  • Optional digital down converter (DDC):
    • Real or complex decimation
    • Decimation by 2, 4, 8, 16, and 32
    • 32-bit NCO
  • Serial LVDS (SLVDS) interface (2-, 1-, and 1/2-wire)
  • Spectral performance (FIN = 5MHz):
    • SNR: 77.5dBFS
    • SFDR: 84dBc HD2, HD3
    • Non HD23: 91dBc
  • Screening and radiation performance
    • QMLV screening and reliability assurance
    • Total ionizing dose (TID): 300krad (Si)
    • Single event latch-up (SEL): 75MeV-cm2/mg
  • Ambient temperature range: -55°C to 105°C
  • Dual Channel ADC
  • 14-bit 125MSPS
  • Noise floor: -156.9dBFS/Hz
  • Low power consumption: 100mW/ch
  • Latency: 2 clock cycles
  • Clock rate versus voltage reference:
    • External reference: 1MSPS to 125MSPS
    • Internal reference: 100MSPS to 125MSPS
  • 14-Bit, no missing codes
  • Input bandwidth: 200MHz (-3dB)
  • INL: ±2.6LSB; DNL: ±0.9LSB
  • Optional digital down converter (DDC):
    • Real or complex decimation
    • Decimation by 2, 4, 8, 16, and 32
    • 32-bit NCO
  • Serial LVDS (SLVDS) interface (2-, 1-, and 1/2-wire)
  • Spectral performance (FIN = 5MHz):
    • SNR: 77.5dBFS
    • SFDR: 84dBc HD2, HD3
    • Non HD23: 91dBc

Description

The ADC3664-SP is a low latency, low noise, and ultra low power, 14-bit, 125MSPS, high-speed dual channel ADC. Designed for best noise performance, the device delivers a noise spectral density of –156.9dBFS/Hz combined with excellent linearity and dynamic range. The ADC3664-SP offers DC precision together with IF sampling support to enable the design of a wide range of applications. The low latency architecture (as low as 1 clock cycle latency) and high sample rate also enable high speed control loops. The ADC consumes only 100mW/ch at 125MSPS and the power consumption scales well with sampling rate.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device also integrates a digital down converter (DDC) to help reduce the data rate and lower system power consumption. The device is pin-to-pin compatible with the 18-bit, 65MSPS ADC3683-SP. The device comes in a 64-pin CFP package (10.9mm x 10.9mm) and supports a temperature range from –55°C to +105°C.

Subscribe to Welllinkchips !
Your Name
* Email
Popular Posts
Featured Parts More >
Submit a request
CONTACT US
Company address

WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK

Send Enquiry
SEND e-MAIL
Office hour from 9am to 6pm ,
Monday through Friday, UTC/GMT +8