AM3358-EP

ACTIVE

Sitara processor: Arm Cortex-A8, 3D, PRU-ICSS, HiRel, CAN

Texas Instruments AM3358-EP Product Info

1 April 2026 1

Parameters

CPU	1 Arm Cortex-A8
Frequency (MHz)	800
Graphics acceleration	1 3D
Display type	1 LCD
Protocols	Ethernet, ICSS, Profibus, Profinet
Features	General purpose
Operating system	Linux, RTOS
Rating	HiRel Enhanced Product
Operating temperature range (°C)	-40 to 105

Package

NFBGA (GCZ)-324-225 mm² 15 x 15

Features

Up to 800-MHz Sitara™ ARM^® Cortex^®-A8 32‑bit RISC processor
- NEON™ SIMD coprocessor
- 32KB of L1 instruction and 32KB of data cache with single-error detection (parity)
- 256KB of L2 cache with error correcting code (ECC)
- 176KB of on-chip boot ROM
- 64KB of dedicated RAM
- Emulation and debug - JTAG
- Interrupt controller (up to 128 interrupt requests)
On-chip memory (shared L3 RAM)
- 64KB of general-purpose on-chip memory controller (OCMC) RAM
- Accessible to all masters
- Supports retention for fast wakeup
External memory interfaces (EMIF)
- mDDR(LPDDR), DDR2, DDR3, DDR3L controller:
  - mDDR: 200-MHz clock (400-MHz data rate)
  - DDR2: 266-MHz clock (532-MHz data rate)
  - DDR3: 400-MHz clock (800-MHz data rate)
  - DDR3L: 400-MHz clock (800-MHz data rate)
  - 16-bit data bus
  - 1GB of total addressable space
  - Supports one x16 or two x8 memory device configurations
- General-purpose memory controller (GPMC)
  - Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, SRAM)
  - Uses BCH code to support 4-, 8-, or 16-bit ECC
  - Uses hamming code to support 1-bit ECC
- Error locator module (ELM)
  - Used in conjunction with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
  - Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
Programmable real-time unit subsystem and industrial communication sSubsystem (PRU-ICSS)
- Supports protocols such as PROFIBUS, PROFINET, EtherNet/IP™, and more
- Two programmable real-time units (PRUs)
  - 32-bit load/store RISC processor capable of running at 200 MHz
  - 8KB of instruction RAM with single-error detection (parity)
  - 8KB of data RAM with single-error detection (parity)
  - Single-cycle 32-bit multiplier with 64-bit accumulator
  - Enhanced GPIO module provides shift-in/out support and parallel latch on external signal
- 12KB of shared RAM with single-error detection (parity)
- Three 120-byte register banks accessible by each PRU
- Interrupt controller (INTC) for handling system input events
- Local interconnect bus for connecting internal and external masters to the resources inside the PRU-ICSS
- Peripherals inside the PRU-ICSS:
  - One UART port with flow control pins, supports up to 12 Mbps
  - One enhanced capture (eCAP) module
  - Two MII Ethernet ports that support industrial ethernet
  - One MDIO port
Power, reset, and clock management (PRCM) module
- Controls the entry and exit of stand-by and deep-sleep modes
- Responsible for sleep sequencing, power domain switch-off sequencing, wake-up sequencing, and power domain switch-on sequencing
- Clocks
  - Integrated 15- to 35-MHz high-frequency oscillator used to generate a reference clock for various system and peripheral clocks
  - Supports individual clock enable and disable control for subsystems and peripherals to facilitate reduced power consumption
  - Five ADPLLs to generate system clocks (MPU subsystem, DDR interface, USB and peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], LCD pixel clock)
- Power
  - Two nonswitchable power domains (real-time clock [RTC], wake-up logic [WAKEUP])
  - Three switchable power domains (MPU subsystem [MPU], SGX530 [GFX], peripherals and infrastructure [PER])
  - Implements SmartReflex™ class 2B for core voltage scaling based on die temperature, process variation, and performance (adaptive voltage scaling [AVS])
  - Dynamic voltage frequency scaling (DVFS)
Real-time clock (RTC)
- Real-time date (Day-Month-Year-Day of Week) and time (Hours-Minutes-Seconds) information
- Internal 32.768-kHz oscillator, RTC logic and 1.1-V internal LDO
- Independent power-on-reset (RTC_PWRONRSTn) input
- Dedicated input pin (EXT_WAKEUP) for external wake events
- Programmable alarm can be used to generate internal interrupts to the PRCM (for wakeup) or Cortex-A8 (for event notification)
- Programmable alarm can be used with external output (PMIC_POWER_EN) to enable the power management IC to restore non-RTC power domains
Peripherals
- Up to two USB 2.0 High-Speed DRD (Dual-Role Device) ports with integrated PHY
- Up to two industrial gigabit ethernet MACs (10, 100, 1000 Mbps)
  - Integrated switch
  - Each MAC supports MII, RMII, RGMII, and MDIO interfaces
  - Ethernet MACs and switch can operate independent of other functions
  - IEEE 1588v2 precision time protocol (PTP)
- Up to two controller-area network (CAN) ports
  - Supports CAN version 2 parts A and B
- Up to two multichannel audio serial ports (McASPs)
  - Transmit and receive clocks up to 50 MHz
  - Up to four serial data pins per McASP port with independent TX and RX clocks
  - Supports time division multiplexing (TDM), inter-IC sound (I2S), and similar formats
  - Supports digital audio interface transmission (SPDIF, IEC60958-1, and AES-3 formats)
  - FIFO buffers for transmit and receive (256 bytes)
- Up to six UARTs
  - All UARTs support IrDA and CIR modes
  - All UARTs support RTS and CTS flow control
  - UART1 supports full modem control
- Up to two master and slave McSPI serial interfaces
  - Up to two chip selects
  - Up to 48 MHz
- Up to three MMC, SD, SDIO ports
  - 1-, 4-, and 8-bit MMC, SD, SDIO modes
  - MMCSD0 has dedicated power rail for 1.8‑V or 3.3-V operation
  - Up to 48-MHz data transfer rate
  - Supports card detect and write protect
  - Complies with MMC4.3, SD, SDIO 2.0 specifications
- Up to three I²C master and slave interfaces
  - Standard mode (up to 100 kHz)
  - Fast mode (up to 400 kHz)
- Up to four banks of general-purpose I/O (GPIO) pins
  - 32 GPIO pins per bank (multiplexed with other functional pins)
  - GPIO pins can be used as interrupt inputs (up to two interrupt inputs per bank)
- Up to three external DMA event inputs that can also be used as interrupt inputs
- Eight 32-bit general-purpose timers
  - DMTIMER1 is a 1-ms timer used for operating system (OS) ticks
  - DMTIMER4–DMTIMER7 are pinned out
- One watchdog timer
- SGX530 3D graphics engine
  - Tile-based architecture delivering up to 20 million polygons per second
  - Universal scalable shader engine (USSE) is a multithreaded engine incorporating pixel and vertex shader functionality
  - Advanced shader feature set in excess of Microsoft VS3.0, PS3.0, and OGL2.0
  - Industry standard API support of Direct3D mobile, OGL-ES 1.1 and 2.0, and OpenMax
  - Fine-grained task switching, load balancing, and power management
  - Advanced geometry DMA-driven operation for minimum CPU interaction
  - Programmable high-quality image anti-aliasing
  - Fully virtualized memory addressing for OS operation in a unified memory architecture
- LCD controller
  - Up to 24-bit data output; 8 bits per pixel (RGB)
  - Resolution up to 2048 × 2048 (with maximum 126-MHz pixel clock)
  - Integrated LCD interface display driver (LIDD) controller
  - Integrated raster controller
  - Integrated DMA engine to pull data from the external frame buffer without burdening the processor via interrupts or a firmware timer
  - 512-word deep internal FIFO
  - Supported display types:
    - Character displays - uses LIDD controller to program these displays
    - Passive matrix LCD displays - uses LCD raster display controller to provide timing and data for constant graphics refresh to a passive display
    - Active matrix LCD displays - uses external frame buffer space and the internal DMA engine to drive streaming data to the panel
- 12-bit successive approximation register (SAR) ADC
  - 200K samples per second
  - Input can be selected from any of the eight analog inputs multiplexed through an 8:1 analog switch
  - Can be configured to operate as a 4-Wire, 5-Wire, or 8-Wire resistive touch screen controller (TSC) interface
- Up to three 32-bit eCAP modules
  - Configurable as three capture inputs or three auxiliary PWM outputs
- Up to three enhanced high-resolution PWM modules (eHRPWMs)
  - Dedicated 16-bit time-base counter with time and frequency controls
  - Configurable as six single-ended, six dual-edge symmetric, or three dual-edge asymmetric outputs
- Up to three 32-bit enhanced quadrature encoder pulse (eQEP) modules
Device identification
- Contains electrical fuse farm (FuseFarm) of which some bits are factory programmable
  - Production ID
  - Device part number (unique JTAG ID)
  - Device revision (readable by host ARM)
Debug interface support
- JTAG and cJTAG for ARM (Cortex-A8 and PRCM)
- Supports device boundary scan
- Supports IEEE 1500
DMA
- On-chip enhanced DMA controller (EDMA) has three third-party transfer controllers (TPTCs) and one third-party channel controller (TPCC), which supports up to 64 programmable logical channels and eight QDMA channels. EDMA is used for:
  - Transfers to and from on-chip memories
  - Transfers to and from external storage (EMIF, GPMC, slave peripherals)
Inter-processor communication (IPC)
- Integrates hardware-based mailbox for IPC and spinlock for process synchronization between Cortex-A8, PRCM, and PRU-ICSS
  - Mailbox registers that generate interrupts
    - Initiators (Cortex-A8, PRCM)
  - Spinlock has 128 software-assigned lock registers
Security
- Crypto hardware accelerators (AES, SHA, PKA, RNG)
Boot modes
- Boot mode is selected through boot configuration pins latched on the rising edge of the PWRONRSTn reset input pin
Package:
- 324-pin S-PBGA-N324 package
  (GCZ suffix), 0.80-mm ball pitch

Up to 800-MHz Sitara™ ARM^® Cortex^®-A8 32‑bit RISC processor
- NEON™ SIMD coprocessor
- 32KB of L1 instruction and 32KB of data cache with single-error detection (parity)
- 256KB of L2 cache with error correcting code (ECC)
- 176KB of on-chip boot ROM
- 64KB of dedicated RAM
- Emulation and debug - JTAG
- Interrupt controller (up to 128 interrupt requests)
On-chip memory (shared L3 RAM)
- 64KB of general-purpose on-chip memory controller (OCMC) RAM
- Accessible to all masters
- Supports retention for fast wakeup
External memory interfaces (EMIF)
- mDDR(LPDDR), DDR2, DDR3, DDR3L controller:
  - mDDR: 200-MHz clock (400-MHz data rate)
  - DDR2: 266-MHz clock (532-MHz data rate)
  - DDR3: 400-MHz clock (800-MHz data rate)
  - DDR3L: 400-MHz clock (800-MHz data rate)
  - 16-bit data bus
  - 1GB of total addressable space
  - Supports one x16 or two x8 memory device configurations
- General-purpose memory controller (GPMC)
  - Flexible 8-bit and 16-bit asynchronous memory interface with up to seven chip selects (NAND, NOR, Muxed-NOR, SRAM)
  - Uses BCH code to support 4-, 8-, or 16-bit ECC
  - Uses hamming code to support 1-bit ECC
- Error locator module (ELM)
  - Used in conjunction with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
  - Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
Programmable real-time unit subsystem and industrial communication sSubsystem (PRU-ICSS)
- Supports protocols such as PROFIBUS, PROFINET, EtherNet/IP™, and more
- Two programmable real-time units (PRUs)
  - 32-bit load/store RISC processor capable of running at 200 MHz
  - 8KB of instruction RAM with single-error detection (parity)
  - 8KB of data RAM with single-error detection (parity)
  - Single-cycle 32-bit multiplier with 64-bit accumulator
  - Enhanced GPIO module provides shift-in/out support and parallel latch on external signal
- 12KB of shared RAM with single-error detection (parity)
- Three 120-byte register banks accessible by each PRU
- Interrupt controller (INTC) for handling system input events
- Local interconnect bus for connecting internal and external masters to the resources inside the PRU-ICSS
- Peripherals inside the PRU-ICSS:
  - One UART port with flow control pins, supports up to 12 Mbps
  - One enhanced capture (eCAP) module
  - Two MII Ethernet ports that support industrial ethernet
  - One MDIO port
Power, reset, and clock management (PRCM) module
- Controls the entry and exit of stand-by and deep-sleep modes
- Responsible for sleep sequencing, power domain switch-off sequencing, wake-up sequencing, and power domain switch-on sequencing
- Clocks
  - Integrated 15- to 35-MHz high-frequency oscillator used to generate a reference clock for various system and peripheral clocks
  - Supports individual clock enable and disable control for subsystems and peripherals to facilitate reduced power consumption
  - Five ADPLLs to generate system clocks (MPU subsystem, DDR interface, USB and peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], LCD pixel clock)
- Power
  - Two nonswitchable power domains (real-time clock [RTC], wake-up logic [WAKEUP])
  - Three switchable power domains (MPU subsystem [MPU], SGX530 [GFX], peripherals and infrastructure [PER])
  - Implements SmartReflex™ class 2B for core voltage scaling based on die temperature, process variation, and performance (adaptive voltage scaling [AVS])
  - Dynamic voltage frequency scaling (DVFS)
Real-time clock (RTC)
- Real-time date (Day-Month-Year-Day of Week) and time (Hours-Minutes-Seconds) information
- Internal 32.768-kHz oscillator, RTC logic and 1.1-V internal LDO
- Independent power-on-reset (RTC_PWRONRSTn) input
- Dedicated input pin (EXT_WAKEUP) for external wake events
- Programmable alarm can be used to generate internal interrupts to the PRCM (for wakeup) or Cortex-A8 (for event notification)
- Programmable alarm can be used with external output (PMIC_POWER_EN) to enable the power management IC to restore non-RTC power domains
Peripherals
- Up to two USB 2.0 High-Speed DRD (Dual-Role Device) ports with integrated PHY
- Up to two industrial gigabit ethernet MACs (10, 100, 1000 Mbps)
  - Integrated switch
  - Each MAC supports MII, RMII, RGMII, and MDIO interfaces
  - Ethernet MACs and switch can operate independent of other functions
  - IEEE 1588v2 precision time protocol (PTP)
- Up to two controller-area network (CAN) ports
  - Supports CAN version 2 parts A and B
- Up to two multichannel audio serial ports (McASPs)
  - Transmit and receive clocks up to 50 MHz
  - Up to four serial data pins per McASP port with independent TX and RX clocks
  - Supports time division multiplexing (TDM), inter-IC sound (I2S), and similar formats
  - Supports digital audio interface transmission (SPDIF, IEC60958-1, and AES-3 formats)
  - FIFO buffers for transmit and receive (256 bytes)
- Up to six UARTs
  - All UARTs support IrDA and CIR modes
  - All UARTs support RTS and CTS flow control
  - UART1 supports full modem control
- Up to two master and slave McSPI serial interfaces
  - Up to two chip selects
  - Up to 48 MHz
- Up to three MMC, SD, SDIO ports
  - 1-, 4-, and 8-bit MMC, SD, SDIO modes
  - MMCSD0 has dedicated power rail for 1.8‑V or 3.3-V operation
  - Up to 48-MHz data transfer rate
  - Supports card detect and write protect
  - Complies with MMC4.3, SD, SDIO 2.0 specifications
- Up to three I²C master and slave interfaces
  - Standard mode (up to 100 kHz)
  - Fast mode (up to 400 kHz)
- Up to four banks of general-purpose I/O (GPIO) pins
  - 32 GPIO pins per bank (multiplexed with other functional pins)
  - GPIO pins can be used as interrupt inputs (up to two interrupt inputs per bank)
- Up to three external DMA event inputs that can also be used as interrupt inputs
- Eight 32-bit general-purpose timers
  - DMTIMER1 is a 1-ms timer used for operating system (OS) ticks
  - DMTIMER4–DMTIMER7 are pinned out
- One watchdog timer
- SGX530 3D graphics engine
  - Tile-based architecture delivering up to 20 million polygons per second
  - Universal scalable shader engine (USSE) is a multithreaded engine incorporating pixel and vertex shader functionality
  - Advanced shader feature set in excess of Microsoft VS3.0, PS3.0, and OGL2.0
  - Industry standard API support of Direct3D mobile, OGL-ES 1.1 and 2.0, and OpenMax
  - Fine-grained task switching, load balancing, and power management
  - Advanced geometry DMA-driven operation for minimum CPU interaction
  - Programmable high-quality image anti-aliasing
  - Fully virtualized memory addressing for OS operation in a unified memory architecture
- LCD controller
  - Up to 24-bit data output; 8 bits per pixel (RGB)
  - Resolution up to 2048 × 2048 (with maximum 126-MHz pixel clock)
  - Integrated LCD interface display driver (LIDD) controller
  - Integrated raster controller
  - Integrated DMA engine to pull data from the external frame buffer without burdening the processor via interrupts or a firmware timer
  - 512-word deep internal FIFO
  - Supported display types:
    - Character displays - uses LIDD controller to program these displays
    - Passive matrix LCD displays - uses LCD raster display controller to provide timing and data for constant graphics refresh to a passive display
    - Active matrix LCD displays - uses external frame buffer space and the internal DMA engine to drive streaming data to the panel
- 12-bit successive approximation register (SAR) ADC
  - 200K samples per second
  - Input can be selected from any of the eight analog inputs multiplexed through an 8:1 analog switch
  - Can be configured to operate as a 4-Wire, 5-Wire, or 8-Wire resistive touch screen controller (TSC) interface
- Up to three 32-bit eCAP modules
  - Configurable as three capture inputs or three auxiliary PWM outputs
- Up to three enhanced high-resolution PWM modules (eHRPWMs)
  - Dedicated 16-bit time-base counter with time and frequency controls
  - Configurable as six single-ended, six dual-edge symmetric, or three dual-edge asymmetric outputs
- Up to three 32-bit enhanced quadrature encoder pulse (eQEP) modules
Device identification
- Contains electrical fuse farm (FuseFarm) of which some bits are factory programmable
  - Production ID
  - Device part number (unique JTAG ID)
  - Device revision (readable by host ARM)
Debug interface support
- JTAG and cJTAG for ARM (Cortex-A8 and PRCM)
- Supports device boundary scan
- Supports IEEE 1500
DMA
- On-chip enhanced DMA controller (EDMA) has three third-party transfer controllers (TPTCs) and one third-party channel controller (TPCC), which supports up to 64 programmable logical channels and eight QDMA channels. EDMA is used for:
  - Transfers to and from on-chip memories
  - Transfers to and from external storage (EMIF, GPMC, slave peripherals)
Inter-processor communication (IPC)
- Integrates hardware-based mailbox for IPC and spinlock for process synchronization between Cortex-A8, PRCM, and PRU-ICSS
  - Mailbox registers that generate interrupts
    - Initiators (Cortex-A8, PRCM)
  - Spinlock has 128 software-assigned lock registers
Security
- Crypto hardware accelerators (AES, SHA, PKA, RNG)
Boot modes
- Boot mode is selected through boot configuration pins latched on the rising edge of the PWRONRSTn reset input pin
Package:
- 324-pin S-PBGA-N324 package
  (GCZ suffix), 0.80-mm ball pitch

Description

The AM3358-EP microprocessor, based on the ARM Cortex-A8 processor, is enhanced with image, graphics processing, peripherals and industrial interface options such as PROFIBUS. The device supports high-level operating systems (HLOS). Linux^® and Android™ are available free of charge from TI.

The AM3358-EP microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AM3358-EP microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

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ELECTRONIC COMPONENTS
All In One Distributor

AM3358-EP

Sitara processor: Arm Cortex-A8, 3D, PRU-ICSS, HiRel, CAN

Texas Instruments AM3358-EP Product Info

Parameters

Package

Features

Description

SUBMITTED SUCCESSFULLY！

ELECTRONIC COMPONENTS All In One Distributor

AM3358-EP

Sitara processor: Arm Cortex-A8, 3D, PRU-ICSS, HiRel, CAN

Texas Instruments AM3358-EP Product Info

Parameters

Package

Features

Description

SUBMITTED SUCCESSFULLY！

ELECTRONIC COMPONENTS
All In One Distributor