0
Sample rate (max) (Msps) |
250 |
Resolution (Bits) |
14 |
Number of input channels |
2 |
Interface type |
DDR LVDS, QDR LVDS |
Analog input BW (MHz) |
900 |
Features |
High Performance |
Rating |
Catalog |
Peak-to-peak input voltage range (V) |
2.5 |
Power consumption (typ) (mW) |
1640 |
Architecture |
Pipeline |
SNR (dB) |
74.9 |
ENOB (Bits) |
11.93 |
SFDR (dB) |
90 |
Operating temperature range (°C) |
-40 to 85 |
Input buffer |
Yes |
VQFN (RGC)-64-81 mm² 9 x 9
The ADS42LB49 and ADS42LB69 are a family of high-linearity, dual-channel, 14- and 16-bit,
250-MSPS, analog-to-digital converters (ADCs) supporting DDR and QDR LVDS output interfaces. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS42LBx9 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with low-power consumption.