0
ACTIVE
Sample rate (max) (Msps) |
125 |
Resolution (Bits) |
14 |
Number of input channels |
2 |
Interface type |
Serial LVDS |
Analog input BW (MHz) |
540 |
Features |
Low Power |
Rating |
Catalog |
Peak-to-peak input voltage range (V) |
2 |
Power consumption (typ) (mW) |
232 |
Architecture |
Pipeline |
SNR (dB) |
73.3 |
ENOB (Bits) |
11.8 |
SFDR (dB) |
94 |
Operating temperature range (°C) |
-50 to 105 |
Input buffer |
No |
VQFN (RGZ)-48-49 mm² 7 x 7
The ADC3244E is a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS analog-to-digital converter (ADC). The device is designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design, and the SYSREF input enables complete system synchronization.
The ADC3244E supports serial, low-voltage, differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where the data from each ADC are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
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