0
ACTIVE
Sample rate (max) (Msps) |
155 |
Resolution (Bits) |
14 |
Number of input channels |
1 |
Interface type |
Parallel CMOS |
Analog input BW (MHz) |
1100 |
Features |
High Performance |
Rating |
Catalog |
Peak-to-peak input voltage range (V) |
2 |
Power consumption (typ) (mW) |
967 |
Architecture |
Pipeline |
SNR (dB) |
72.3 |
ENOB (Bits) |
11.6 |
SFDR (dB) |
89.7 |
Operating temperature range (°C) |
-40 to 85 |
Input buffer |
No |
WQFN (RHS)-48-49 mm² 7 x 7
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The ADC14155 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 967 mW of power at 155 MSPS.
The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation.
The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14155 can be operated with an external reference.
The ADC14155 can be configured for either single-ended or differential operation. Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC14155 is available in a 48-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.