The STM32F303RBT6 targets the practical center of the 64-pin F303 range: 128 KB of Flash and 32 KB of SRAM paired with four 5 MSPS 12-bit ADCs, four PGA-capable operational amplifiers, seven comparators, and dual 12-bit DACs, all in a 10 mm × 10 mm LQFP with 52 I/O. Rather than pursuing maximum memory density, the RBT6 is configured for designs where the analog signal chain and the control peripherals are the dominant requirements, and the firmware image—though substantial—remains within a predictable footprint. This balance places it at the center of single-axis motor drives, digital power stages, and multi-channel sensor interfaces that benefit from hardware signal conditioning but do not require the 256 KB code space of the largest 64-pin variant.

The RBT6’s analog architecture is defined by the integration of amplification and comparison alongside conversion. The four 12-bit ADCs sample at 5 MSPS with a 0.20 μs conversion time, and each supports selectable resolution of 12, 10, 8, or 6 bits as well as single-ended or differential input configurations. The four operational amplifiers operate in PGA mode with internal gains of ×2, ×4, ×8, and ×16, and every terminal is brought out to a pin so that external filtering or feedback components can be added around the internal gain stage. In a shunt-based current-sensing path, this eliminates the discrete amplifier that would otherwise be required between the shunt and the ADC input, reducing component count and board area while preserving signal integrity.

The seven comparators complement the ADC path by providing event detection that does not depend on firmware timing. With rail-to-rail inputs and response times in the nanosecond range, they can be connected directly to the break inputs of the advanced-control timers. When a phase current exceeds a programmed threshold, the comparator output transitions, the timer disables the PWM outputs in hardware, and the protection path completes without CPU intervention. This architecture is central to the RBT6’s suitability for inverter and motor-drive applications, where software-based over-current response would be too slow to protect the power stage.

Table 1 presents the RBT6’s analog resource profile in a compact reference format.

The 128 KB Flash and 32 KB SRAM configuration of the RBT6 is supported by 8 KB of CCM SRAM on the instruction and data buses, with hardware parity checking. The CCM provides a deterministic execution region for routines that cannot tolerate Flash wait states: the current-control loop in a motor drive, the compensator in a digital power supply, or the high-priority interrupt handlers in a multi-channel acquisition system. ST’s characterization of the F303 architecture indicates up to 90 DMIPS when code executes from CCM, and the practical effect is that a 72 MHz RBT6 can sustain a higher PWM frequency or a shorter control-loop latency than the same core executing from Flash.

The 32 KB SRAM is sufficient for a single-axis FOC implementation, including ADC buffers, communication stacks (CAN or USB), and a bootloader, provided that buffer sizes are chosen with awareness of the total budget. Hardware parity checking on the first 16 KB of SRAM adds a layer of runtime fault detection that is valuable in safety-adjacent motor and power applications.

The RBT6 includes two advanced-control 16-bit timers, each capable of generating up to six PWM outputs with dead-time insertion and emergency stop inputs. These timers can trigger the ADCs at specific points within the PWM period, synchronizing current sampling with the switching waveform so that measurements are taken in the quietest portion of the cycle. The timer resolution is fine enough to support PWM frequencies in the tens of kilohertz with high duty-cycle granularity, and the complementary outputs with programmable dead time interface directly to half-bridge gate drivers.

A 32-bit general-purpose timer and several 16-bit timers provide additional PWM channels, input capture for encoder or Hall-sensor interfaces, and pulse-counting capability. The two 16-bit basic timers can drive the DACs, enabling synchronized analog output generation alongside the PWM and ADC activity. This timer density allows the RBT6 to coordinate a power stage, a position feedback interface, and auxiliary control signals without external logic.

The RBT6’s position within the 64-pin F303 family is defined by memory capacity. The RCT6 offers 256 KB Flash and 40 KB SRAM with an otherwise identical peripheral set and pinout. The RBT6 is the appropriate choice when the firmware image—including the motor-control library, the communication stack, and the application layer—is expected to remain within approximately 128 KB of Flash and the SRAM demand does not require the additional 8 KB available on the larger-memory variant. A single-axis sensorless FOC drive with a CAN or UART host interface and a modest diagnostic layer is a representative fit. A digital power converter with soft-start profiles, protection thresholds, and PMBus communication also aligns with the RBT6’s memory envelope.

The shared LQFP64 pinout across the RBT6 and RCT6 supports a production strategy in which the RBT6 is used for baseline configurations and the RCT6 is reserved for feature-expanded variants. Because the analog front-end, timer allocation, and communication pin mapping remain constant, the transition requires only a Bill-of-Materials change and a firmware recompile against the larger memory map, without a PCB redesign.

In motor control, the RBT6’s PGAs and comparators map directly onto the signal chain of a three-phase inverter. Three shunt resistors produce bidirectional voltage drops; the PGAs amplify these signals with a fixed gain; the ADCs sample the amplified currents and the bus voltage; the comparators provide cycle-by-cycle over-current limiting routed to the timer break inputs. ST’s dual-motor FOC library supports the STM32F303xB/C devices, and the RBT6’s 128 KB Flash is sufficient for a single-axis implementation of that library alongside application code. The STEVAL-CTM010V1 reference design, which uses an STM32F303RB to control two sensorless motor drives plus a digital PFC stage, demonstrates the RBT6’s capability in a multi-function power-control architecture.

Digital power conversion is a second natural domain. The 5 MSPS ADCs capture inductor current and output voltage with sufficient bandwidth to implement average-current-mode or peak-current-mode control, while the comparators provide fast over-voltage and over-current trips. The advanced-control timers generate the PWM signals for buck, boost, or flyback topologies, and the 128 KB Flash accommodates the control loop, soft-start sequencing, and a communication interface such as PMBus or CAN. Uninterruptible power supplies, battery chargers, and LED drivers share these architectural requirements.

A third application area is multi-channel industrial sensing. The four parallel ADCs allow simultaneous sampling of several analog quantities—pressure, flow, temperature, and supply voltage, for example—without external sample-and-hold circuitry. The PGAs condition low-level bridge or thermocouple signals, and the comparators implement threshold alarms in hardware. The 52-pin I/O budget supports the serial interfaces (I²C, SPI, USART) needed to connect a local sensor cluster and report aggregated data to a host controller.

The RBT6 is supported by the STM32CubeF3 firmware package and STM32CubeIDE, with HAL and LL drivers covering the ADC, PGA, comparator, DAC, and timer peripherals. The X-CUBE-MCSDK motor-control workbench generates configuration code for the PGA gains, ADC trigger timing, and comparator thresholds used in FOC applications, reducing the manual register-level effort for the most timing-sensitive peripheral interactions.

Hardware evaluation can begin on the NUCLEO-F303RE, a 64-pin LQFP development board that exposes the F303 peripheral set through Arduino Uno V3 and ST morpho connectors. Although the NUCLEO board carries the 512 KB STM32F303RET6, the analog and timer architecture is representative of the RBT6, allowing the signal chain and control firmware to be validated before a custom board is fabricated. Two layout considerations deserve early attention: the analog supply (VDDA) should be decoupled with low-ESR capacitors and fed from a quiet source rather than the digital 3.3 V rail, and the PGA and comparator input pins should be allocated before the communication peripherals, because their pin-sharing constraints are less flexible than those of the digital interfaces. With these practices, the STM32F303RBT6 delivers the full F303 mixed-signal capability in a memory configuration that matches the majority of single-axis motor, digital power, and multi-channel sensing designs.