AD9694S

RECOMMENDED FOR NEW DESIGNS

14-Bit, 500 MSPS, JESD204B, Quad Analog-to-Digital Converter

Analog Devices AD9694S Product Info

10 February 2026 6

Features

JESD204B (Subclass 1) coded serial digital outputs
- Lane rates up to 15 Gbps
1.66 W total power at 500 MSPS
- 415 mW per ADC channel
SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range)
SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range)
Noise density = −151.5 dBFS/Hz (1.80 V p-p input range)
0.975 V, 1.8 V, and 2.5 V dc supply operation
No missing codes
Internal ADC voltage reference
Analog input buffer
On-chip dithering to improve small signal linearity
Flexible differential input voltage range
- 1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)
1.4 GHz analog input full power bandwidth
Amplitude detect bits for efficient AGC implementation
4 integrated wideband digital processors
- 48-bit NCO, up to 4 cascaded half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
On-chip temperature diode
Flexible JESD204B lane configurations

COMMERCIAL SPACE FEATURES

Supports aerospace applications
Wafer diffusion lot traceability
Radiation monitors
- Total ionizing dose (TID)
Outgassing characterization

Part details & applications

The AD9694S-CSL is a quad, 14-bit, 500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sampleand- hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 1.4 GHz. The AD9694S-CSL is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.

The analog inputs and clock signals are differential inputs. Each pair of ADC data outputs is internally connected to two digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters. In addition to the DDC blocks, the AD9694S-CSL has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.

Users can configure each pair of intermediate frequency (IF) receiver outputs onto either one or two lanes of Subclass 1 JESD204Bbased high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.

The AD9694S-CS

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