0
ACTIVE
Number of channels |
1 |
Isolation rating |
Reinforced |
Power switch |
IGBT, SiCFET |
Withstand isolation voltage (VISO) (Vrms) |
5700 |
Working isolation voltage (VIOWM) (Vrms) |
1500 |
Transient isolation voltage (VIOTM) (VPK) |
8000, 8400 |
Peak output current (A) |
10 |
Peak output current (source) (typ) (A) |
10 |
Peak output current (sink) (typ) (A) |
10 |
Features |
Active miller clamp, Fault reporting, Integrated analog to PWM sensor, Over Current Protection, Power good, Short circuit protection, Soft turn-off |
Output VCC/VDD (min) (V) |
13 |
Output VCC/VDD (max) (V) |
33 |
Input supply voltage (min) (V) |
3 |
Input supply voltage (max) (V) |
5.5 |
Propagation delay time (µs) |
0.09 |
Input threshold |
CMOS |
Operating temperature range (°C) |
-40 to 125 |
Rating |
Automotive |
Bootstrap supply voltage (max) (V) |
2121 |
Rise time (ns) |
33 |
Fall time (ns) |
27 |
Undervoltage lockout (typ) (V) |
12 |
TI functional safety category |
Functional Safety Quality-Managed |
SOIC (DW)-16-106.09 mm² 10.3 x 10.3
The UCC21710-Q1 is a galvanic isolated single channel gate driver designed for up to 1700-V SiC MOSFETs and IGBTs with advanced protection features, best-in-class dynamic performance and robustness. UCC21710-Q1 has up to ±10A peak source and sink current.
The input side is isolated from the output side with SiO2 capacitive isolation technology, supporting up to 1.5kVRMS working voltage, 12.8kVPK surge immunity with longer than 40 years Isolation barrier life, as well as providing low part-to-part skew , and >150V/ns common mode noise immunity (CMTI).
The UCC21710-Q1 includes the state-of-the-art protection features, such as fast overcurrent and short circuit detection, shunt current sensing support, fault reporting, active Miller clamp, and input and output side power supply UVLO to optimize SiC and IGBT switching behavior and robustness. The isolated analog to PWM sensor can be used for easier temperature or voltage sensing, further increasing the drivers versatility and simplifying the system design effort, size and cost.