Product
0
TL16C752D
  • TL16C752D
  • TL16C752D

TL16C752D

ACTIVE

Dual UART With 64-Byte FIFO

Texas Instruments TL16C752D Product Info

1 April 2026 3

Parameters

Number of channels

2

FIFO (Byte)

64

Rx FIFO trigger levels (#)

16

Tx FIFO trigger levels (#)

16

Programmable FIFO trigger levels

Yes

CPU interface

X86

Baud rate at Vcc = 2.5 V & with 16x sampling (max) (Mbps)

1.5

Baud rate at Vcc = 1.8 V & with 16x sampling (max) (Mbps)

1

Baud rate at Vcc = 3.3 V & with 16x sampling (max) (Mbps)

2

Baud rate at Vcc = 5 V & with 16x sampling (max) (Mbps)

3

Operating voltage (V)

1.62 to 5.5

Auto RTS/CTS

Yes

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Package

TQFP (PFB)-48-81 mm² 9 x 9

Features

  • Pin Compatible With TL16C2550 With Enhanced Features Provided Through an Improved FIFO Register
  • Supports Wide Supply Voltage Range of 1.62 V to 5.5 V
    • 3 Mbps (48-MHz Oscillator Input Clock)
      at 5 V
    • 3 Mbps (48-MHz Oscillator Input Clock)
      at 3.3 V
    • 1.5 Mbps (24-MHz Oscillator Input Clock)
      at 2.5 V
    • 1 Mbps (16-MHz Oscillator Input Clock)
      at 1.8 V
  • Characterized for Operation from –40°C to 85°C
  • 64-Byte Transmit/Receive FIFO
  • Software-Selectable Baud-Rate Generator
  • Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA, Interrupt Generation, and Software or Hardware Flow Control
  • Software/Hardware Flow Control
    • Programmable Xon and Xoff Characters With Optional Xon Any Character
    • Programmable Auto-RTS and Auto-CTS-Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)
  • DMA Signaling Capability for Both Received and Transmitted Data on PN Package
  • RS-485 Mode Support
  • Infrared Data Association (IrDA) Capability
  • Programmable Sleep Mode
  • Programmable Serial Interface Characteristics
    • 5, 6, 7, or 8-Bit Characters With 1, 1.5, or 2 Stop Bit Generation
    • Even, Odd, or No Parity Bit Generation and Detection
  • False Start Bit and Line Break Detection
  • Internal Test and Loopback Capabilities
  • SC16C752B and XR16M752 Pin Compatible With Additional Enhancements
  • Pin Compatible With TL16C2550 With Enhanced Features Provided Through an Improved FIFO Register
  • Supports Wide Supply Voltage Range of 1.62 V to 5.5 V
    • 3 Mbps (48-MHz Oscillator Input Clock)
      at 5 V
    • 3 Mbps (48-MHz Oscillator Input Clock)
      at 3.3 V
    • 1.5 Mbps (24-MHz Oscillator Input Clock)
      at 2.5 V
    • 1 Mbps (16-MHz Oscillator Input Clock)
      at 1.8 V
  • Characterized for Operation from –40°C to 85°C
  • 64-Byte Transmit/Receive FIFO
  • Software-Selectable Baud-Rate Generator
  • Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA, Interrupt Generation, and Software or Hardware Flow Control
  • Software/Hardware Flow Control
    • Programmable Xon and Xoff Characters With Optional Xon Any Character
    • Programmable Auto-RTS and Auto-CTS-Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)
  • DMA Signaling Capability for Both Received and Transmitted Data on PN Package
  • RS-485 Mode Support
  • Infrared Data Association (IrDA) Capability
  • Programmable Sleep Mode
  • Programmable Serial Interface Characteristics
    • 5, 6, 7, or 8-Bit Characters With 1, 1.5, or 2 Stop Bit Generation
    • Even, Odd, or No Parity Bit Generation and Detection
  • False Start Bit and Line Break Detection
  • Internal Test and Loopback Capabilities
  • SC16C752B and XR16M752 Pin Compatible With Additional Enhancements

Description

The TL16C752D is a dual universal asynchronous receiver transmitter (UART) with 64-byte FIFOs, automatic hardware and software flow control, and data rates up to 3 Mbps. The device offers enhanced features. It has a transmission character control register (TCR) that stores received FIFO threshold level to start or stop transmission during hardware and software flow control.

With the FIFO RDY register, the software gets the status of TXRDY or RXRDY for all two ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The TL16C752D incorporates the functionality of two UARTs, each UART having its own register set and FIFOs.

The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is asynchronous communications element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C752D device.

Subscribe to Welllinkchips !
Your Name
* Email
Popular Posts
Featured Parts More >
Submit a request
CONTACT US
Company address

WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK

Send Enquiry
SEND e-MAIL
Office hour from 9am to 6pm ,
Monday through Friday, UTC/GMT +8