0
ACTIVE
Number of channels |
1 |
Technology family |
LVC |
Supply voltage (min) (V) |
1.65 |
Supply voltage (max) (V) |
5.5 |
Input type |
Standard CMOS |
Output type |
Push-Pull |
Clock frequency (max) (MHz) |
200 |
IOL (max) (mA) |
32 |
IOH (max) (mA) |
-32 |
Supply current (max) (µA) |
10 |
Features |
Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
Operating temperature range (°C) |
-40 to 125 |
Rating |
Catalog |
DSBGA (YZP)-8-2.8125 mm² 2.25 x 1.25
This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCC operation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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