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SN74LVC165A-Q1
  • SN74LVC165A-Q1
  • SN74LVC165A-Q1
  • SN74LVC165A-Q1
  • SN74LVC165A-Q1
  • SN74LVC165A-Q1
  • SN74LVC165A-Q1

SN74LVC165A-Q1

ACTIVE

Automotive, 1.1V to 3.6V parallel-load eight-bit shift registers

Texas Instruments SN74LVC165A-Q1 Product Info

1 April 2026 0

Parameters

Technology family

LVC

Supply voltage (min) (V)

1.1

Supply voltage (max) (V)

3.6

Input type

CMOS

Output type

Push-Pull

IOL (max) (mA)

24

IOH (max) (mA)

-24

Features

Over-voltage tolerant inputs, Partial power down (Ioff)

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Package

SOIC (D)-16-59.4 mm² 9.9 x 6

Features

  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Operating range from 1.1V to 3.6V
  • Over-voltage tolerant inputs support up to 5.5V independent of VCC
  • Supports partial-power-down with back drive protection (Ioff)
  • High push-pull output drive strength:

    • ±24mA at 3.3V
    • ±8mA at 2.3V
    • ±4mA at 1.65V
  • Maximum propagation delay of 20ns at 3.3V
  • Latch-up performance exceeds 100mAper JESD78 and AEC-Q100-004
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Operating range from 1.1V to 3.6V
  • Over-voltage tolerant inputs support up to 5.5V independent of VCC
  • Supports partial-power-down with back drive protection (Ioff)
  • High push-pull output drive strength:

    • ±24mA at 3.3V
    • ±8mA at 2.3V
    • ±4mA at 1.65V
  • Maximum propagation delay of 20ns at 3.3V
  • Latch-up performance exceeds 100mAper JESD78 and AEC-Q100-004

Description

The SN74LVC165A-Q1 contains one 8-bit parallel-load shift register. Data is loaded asynchronously using the shift or load (SH/LD) select pin. The device includes a serial (SER) input to allow for daisy chaining, and a standard (QH) and inverted (QH) output.

The SN74LVC165A-Q1 contains one 8-bit parallel-load shift register. Data is loaded asynchronously using the shift or load (SH/LD) select pin. The device includes a serial (SER) input to allow for daisy chaining, and a standard (QH) and inverted (QH) output.

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