0
ACTIVE
Bits (#) |
8 |
Data rate (max) (Mbps) |
150 |
Topology |
Push-Pull |
Direction control (typ) |
Fixed-direction |
Vin (min) (V) |
1.65 |
Vin (max) (V) |
5.5 |
Vout (min) (V) |
1.65 |
Vout (max) (V) |
5.5 |
Applications |
GPIO, SPI |
Features |
Output enable, Single supply |
Prop delay (ns) |
13.7 |
Technology family |
LVxT |
Supply current (max) (mA) |
1.5 |
Rating |
HiRel Enhanced Product |
Operating temperature range (°C) |
-55 to 125 |
TSSOP (PW)-20-41.6 mm² 6.5 x 6.4
Down translation:
The SN74LV8T9541-EP contains eight buffers with 3-state outputs and Schmitt-Trigger inputs. The active low output enable pins (OE1 and OE2) control all eight channels, and are configured so that both must be low for the outputs to be active. When the outputs are enabled, the outputs are actively driven low or high. When the outputs are disabled, the outputs are set into the high-impedance state. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).
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