0
ACTIVE
Bits (#) |
8 |
Data rate (max) (Mbps) |
150 |
Topology |
Push-Pull |
Direction control (typ) |
Fixed-direction |
Vin (min) (V) |
1.65 |
Vin (max) (V) |
5.5 |
Vout (min) (V) |
1.65 |
Vout (max) (V) |
5.5 |
Applications |
GPIO |
Features |
Output enable, Single supply, Wettable flanks package |
Prop delay (ns) |
13.7 |
Technology family |
LVxT |
Supply current (max) (mA) |
1.5 |
Rating |
Automotive |
Operating temperature range (°C) |
-40 to 125 |
TSSOP (PW)-20-41.6 mm² 6.5 x 6.4
Available in Wettable Flanks QFN package
Down translation:
The SN74LV8T244-Q1 is an octal buffer with 3-state outputs and Schmitt-trigger inputs. The device is configured into two banks of four drivers, each controlled by an output enable pin.
The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
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