Product
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SN74LV74A
  • SN74LV74A
  • SN74LV74A
  • SN74LV74A
  • SN74LV74A
  • SN74LV74A
  • SN74LV74A
  • SN74LV74A

SN74LV74A

ACTIVE

Dual Positive-Edge-Triggered D-Type Flip-Flops

Texas Instruments SN74LV74A Product Info

1 April 2026 1

Parameters

Number of channels

2

Technology family

LV-A

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

110

IOL (max) (mA)

12

IOH (max) (mA)

-12

Supply current (max) (µA)

20

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Package

SOIC (D)-14-51.9 mm² 8.65 x 6

Features

  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 8.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down
    Mode Operation
  • Latch-up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 500-V Charged-Device Model (C101)
  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 8.5 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down
    Mode Operation
  • Latch-up Performance Exceeds 250 mA
    Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 500-V Charged-Device Model (C101)

Description

These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation.

These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation.

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