0
Technology family |
LV-A |
Supply voltage (min) (V) |
2 |
Supply voltage (max) (V) |
5.5 |
Number of channels |
3 |
Inputs per channel |
3 |
IOL (max) (mA) |
12 |
IOH (max) (mA) |
-12 |
Input type |
Standard CMOS |
Output type |
Push-Pull |
Features |
Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) |
Data rate (max) (Mbps) |
70 |
Rating |
Catalog |
Operating temperature range (°C) |
-40 to 85 |
SOIC (D)-14-51.9 mm² 8.65 x 6
These triple 3-input positive-NAND gates are designed for 2 V to 5.5 V VCC operation. The SN74LV10A devices perform the Boolean function Y = A • B • C in positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.