Product
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SN74LV125A
  • SN74LV125A
  • SN74LV125A
  • SN74LV125A
  • SN74LV125A
  • SN74LV125A
  • SN74LV125A
  • SN74LV125A
  • SN74LV125A

SN74LV125A

ACTIVE

4-ch, 2-V to 5.5-V buffers with 3-state outputs

Texas Instruments SN74LV125A Product Info

1 April 2026 1

Parameters

Technology family

LV-A

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Number of channels

4

IOL (max) (mA)

16

Supply current (max) (µA)

20

IOH (max) (mA)

-16

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Package

PDIP (N)-14-181.42 mm² 19.3 x 9.4

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6 ns at 5 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model
    • 200-V Machine Model
    • 2000-V Charged-Device Model
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6 ns at 5 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model
    • 200-V Machine Model
    • 2000-V Charged-Device Model

Description

The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.

The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.

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