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SN74HCT240
  • SN74HCT240
  • SN74HCT240
  • SN74HCT240
  • SN74HCT240
  • SN74HCT240
  • SN74HCT240

SN74HCT240

ACTIVE

8-ch, 4.5V to 5.5V inverters with TTL-compatible CMOS inputs and 3-state outputs

Texas Instruments SN74HCT240 Product Info

1 April 2026 0

Parameters

Technology family

HCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

8

IOL (max) (mA)

6

IOH (max) (mA)

-6

Supply current (max) (µA)

80

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Package

PDIP (N)-20-228.702 mm² 24.33 x 9.4

Features

  • Operating voltage range of 4.5V to 5.5V
  • High-current outputs drive up to 15 LSTTL loads
  • Low power consumption, 80µA max ICC
  • Typical tpd = 12 ns
  • ±6mA output drive at 5V
  • Low input current of 1µA max
  • Inputs are TTL-voltage compatible
  • 3-state outputs drive bus lines or buffer memory address registers
  • Operating voltage range of 4.5V to 5.5V
  • High-current outputs drive up to 15 LSTTL loads
  • Low power consumption, 80µA max ICC
  • Typical tpd = 12 ns
  • ±6mA output drive at 5V
  • Low input current of 1µA max
  • Inputs are TTL-voltage compatible
  • 3-state outputs drive bus lines or buffer memory address registers

Description

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

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