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SN74HCS594-Q1
  • SN74HCS594-Q1
  • SN74HCS594-Q1
  • SN74HCS594-Q1
  • SN74HCS594-Q1
  • SN74HCS594-Q1
  • SN74HCS594-Q1

SN74HCS594-Q1

ACTIVE

Automotive 8-bit shift registers with output registers

Texas Instruments SN74HCS594-Q1 Product Info

1 April 2026 0

Parameters

Configuration

Serial-in, Parallel-out

Bits (#)

8

Technology family

HCS

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Schmitt-Trigger

Output type

Push-Pull

Clock frequency (MHz)

68

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

2

Features

Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Package

SOIC (D)-16-59.4 mm² 9.9 x 6

Features

  • AEC-Q100 Qualified for automotive applications:
    • Device temperature grade 1: –40°C to +125°C, T A
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C6
  • Available in wettable flank QFN (WBQB) package
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption:
    • Typical I CC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • AEC-Q100 Qualified for automotive applications:
    • Device temperature grade 1: –40°C to +125°C, T A
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C6
  • Available in wettable flank QFN (WBQB) package
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption:
    • Typical I CC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V

Description

The SN74HCS594-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel outputs. Separate clocks and direct overriding clear ( SRCLR, RCLR) inputs are provided for both the shift and storage register. A serial output (Q H’) is provided for cascading.

Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register is one count pulse ahead of the storage register.

The SN74HCS594-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel outputs. Separate clocks and direct overriding clear ( SRCLR, RCLR) inputs are provided for both the shift and storage register. A serial output (Q H’) is provided for cascading.

Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register is one count pulse ahead of the storage register.

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