0
ACTIVE
Configuration |
Serial-in, Parallel-out |
Bits (#) |
8 |
Technology family |
HC |
Supply voltage (min) (V) |
2 |
Supply voltage (max) (V) |
6 |
Input type |
Standard CMOS |
Output type |
Push-Pull |
Clock frequency (MHz) |
24 |
IOL (max) (mA) |
5.2 |
IOH (max) (mA) |
-5.2 |
Supply current (max) (µA) |
80 |
Features |
Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode |
Operating temperature range (°C) |
-40 to 125 |
Rating |
Catalog |
PDIP (N)-14-181.42 mm² 19.3 x 9.4
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK
