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SN74HC112
  • SN74HC112
  • SN74HC112
  • SN74HC112
  • SN74HC112

SN74HC112

ACTIVE

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset

Texas Instruments SN74HC112 Product Info

1 April 2026 4

Parameters

Number of channels

2

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

LVTTL/CMOS

Output type

Push-Pull

Clock frequency (MHz)

24

Supply current (max) (µA)

40

IOL (max) (mA)

4

IOH (max) (mA)

-4

Features

Balanced outputs, Clear, High speed (tpd 10-50ns), Negative edge triggered, Positive input clamp diode, Preset

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Package

PDIP (N)-16-181.42 mm² 19.3 x 9.4

Features

  • Wide operating voltage range of 2V to 6V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40µA max ICC
  • Typical tpd = 13ns
  • ±4mA output drive at 5V
  • Low input current of 1µA max
  • Wide operating voltage range of 2V to 6V
  • Outputs can drive up to 10 LSTTL loads
  • Low power consumption, 40µA max ICC
  • Typical tpd = 13ns
  • ±4mA output drive at 5V
  • Low input current of 1µA max

Description

The SNx4HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.

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