0
ACTIVE
Bits (#) |
2 |
Data rate (max) (Mbps) |
500 |
Topology |
Push-Pull |
Direction control (typ) |
Direction-controlled |
Vin (min) (V) |
1.2 |
Vin (max) (V) |
3.6 |
Vout (min) (V) |
1.2 |
Vout (max) (V) |
3.6 |
Applications |
I2S |
Features |
Overvoltage tolerant inputs, Partial power down (Ioff) |
Technology family |
AVC |
Supply current (max) (mA) |
0.02 |
Rating |
Automotive, Catalog |
Operating temperature range (°C) |
-40 to 125 |
DSBGA (YZP)-8-2.8125 mm² 2.25 x 1.25
This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2V to 3.6V. The B ports are designed to track VCCB and accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation and level-shifting between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.
The SN74AVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess leakage current on the internal CMOS structure.
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