0
ACTIVE
Technology family |
AUC |
Supply voltage (min) (V) |
0.8 |
Supply voltage (max) (V) |
2.7 |
Number of channels |
1 |
IOL (max) (mA) |
9 |
Supply current (max) (µA) |
10 |
IOH (max) (mA) |
-9 |
Input type |
Standard CMOS |
Output type |
3-State |
Features |
Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) |
Rating |
Catalog |
Operating temperature range (°C) |
-40 to 85 |
DSBGA (YZP)-5-2.1875 mm² 1.75 x 1.25
The SN74AUC1G126 bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUC1G126 device is a single line driver with a tri-state output. The output is disabled when the output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
NanoFree™ package technology is a major breakthrough in device packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, which prevents damaging current backflow through the device when it is powered down.
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