Product
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SN74AHC164-Q1
  • SN74AHC164-Q1
  • SN74AHC164-Q1
  • SN74AHC164-Q1
  • SN74AHC164-Q1
  • SN74AHC164-Q1

SN74AHC164-Q1

ACTIVE

Automotive 8-bit serial-in and parallel-out shift register

Texas Instruments SN74AHC164-Q1 Product Info

1 April 2026 2

Parameters

Configuration

Serial-in

Bits (#)

8

Technology family

AHC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (MHz)

115

IOL (max) (mA)

8

IOH (max) (mA)

-8

Supply current (max) (µA)

40

Features

Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Package

TSSOP (PW)-14-32 mm² 5 x 6.4

Features

  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package
  • Operating range 2V to 5.5V VCC
  • Low delay, 14ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Available in wettable flank QFN package
  • Operating range 2V to 5.5V VCC
  • Low delay, 14ns max (VCC = 5V, CL = 50pF)
  • Latch-up performance exceeds 250mAper JESD 17

Description

The SN74AHC164-Q1 is an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Outputs are directly connected to the internal shift register, resulting in immediate output changes as values are shifted into the register. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.

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