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SN74AC595-Q1
  • SN74AC595-Q1
  • SN74AC595-Q1
  • SN74AC595-Q1
  • SN74AC595-Q1

SN74AC595-Q1

ACTIVE

Automotive 1.5V to 6V eight-bit shift registers with tri-state output registers

Texas Instruments SN74AC595-Q1 Product Info

1 April 2026 0

Parameters

Configuration

Serial-in

Bits (#)

8

Technology family

AC

Supply voltage (min) (V)

1.5

Supply voltage (max) (V)

6

Input type

CMOS

Output type

3-State

Clock frequency (MHz)

90

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

20

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Package

TSSOP (PW)-16-32 mm² 5 x 6.4

Features

  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Wide operating range of 1.5V to 6V
  • Inputs accept voltages up to 6V
  • Continuous ±24mA output drive at 5V
  • Supports up to ±75mA output drive at 5Vin short bursts
  • Drives 50Ω transmission lines
  • Maximum tpd of 12ns at 5V, 50pF load
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • Wide operating range of 1.5V to 6V
  • Inputs accept voltages up to 6V
  • Continuous ±24mA output drive at 5V
  • Supports up to ±75mA output drive at 5Vin short bursts
  • Drives 50Ω transmission lines
  • Maximum tpd of 12ns at 5V, 50pF load

Description

The SN74AC595-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. This configuration allows data to be loaded into the shift register while the outputs remain static. The device includes 3-state outputs to allow for disabling the outputs. The device has a separate shift register output (QH’) for connecting shift registers in series.

The SN74AC595-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. This configuration allows data to be loaded into the shift register while the outputs remain static. The device includes 3-state outputs to allow for disabling the outputs. The device has a separate shift register output (QH’) for connecting shift registers in series.

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