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SN54SC4T125-SEP
  • SN54SC4T125-SEP
  • SN54SC4T125-SEP
  • SN54SC4T125-SEP

SN54SC4T125-SEP

ACTIVE

Radiation-tolerant four-bit fixed-direction level translator

Texas Instruments SN54SC4T125-SEP Product Info

1 April 2026 4

Parameters

Bits (#)

4

Data rate (max) (Mbps)

150

Topology

Push-Pull

Vin (min) (V)

1.2

Vin (max) (V)

5.5

Applications

GPIO

Features

Balanced outputs, Over-voltage tolerant inputs, Single supply

Prop delay (ns)

12.5

Technology family

SCxT

Supply current (max) (mA)

0.093

Rating

Space

Operating temperature range (°C)

-55 to 125

Package

TSSOP (PW)-14-32 mm² 5 x 6.4

Features

  • VID V62/23631-01XE

  • Radiation Tolerant

    • Single Event Latch-Up (SEL) immune up to 43 MeV-cm 2/mg at 125°C

    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)

    • Single Event Transient (SET) characterized up to LET = 43 MeV-cm 2/mg

  • Wide operating range of 1.2 V to 5.5 V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17

  • Space Enhanced Plastic

    • Controlled baseline

    • Au bondwire and NiPdAu lead finish

    • Meets NASA ASTM E595 outgassing specification

    • One fabrication, assembly, and test site

    • Extended product life cycle

    • Product traceability

  • VID V62/23631-01XE

  • Radiation Tolerant

    • Single Event Latch-Up (SEL) immune up to 43 MeV-cm 2/mg at 125°C

    • Total Ionizing Does (TID) Radiation Lot Acceptance Testing (RLAT) for every wafer lot up to 30 krad(Si)

    • Single Event Transient (SET) characterized up to LET = 43 MeV-cm 2/mg

  • Wide operating range of 1.2 V to 5.5 V

  • Single-supply voltage translator:

    • Up translation:

      • 1.2 V to 1.8 V

      • 1.5 V to 2.5 V

      • 1.8 V to 3.3 V

      • 3.3 V to 5.0 V

    • Down translation:

      • 5.0 V, 3.3 V, 2.5 V to 1.8 V
      • 5.0 V, 3.3 V to 2.5 V
      • 5.0 V to 3.3 V
  • 5.5-V tolerant input pins
  • Supports standard pinouts
  • Up to 150 Mbps with 5-V or 3.3-V V CC
  • Latch-up performance exceeds 250 mA per JESD 17

  • Space Enhanced Plastic

    • Controlled baseline

    • Au bondwire and NiPdAu lead finish

    • Meets NASA ASTM E595 outgassing specification

    • One fabrication, assembly, and test site

    • Extended product life cycle

    • Product traceability

Description

The SN54SC4T125-SEP contains four independent buffers with 3-state outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be put into a high impedance (Hi-Z) state by applying a HIGH on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

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