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CDCVF25081
  • CDCVF25081
  • CDCVF25081
  • CDCVF25081

CDCVF25081

ACTIVE

1:8 3.3-V phase lock loop clock driver

Texas Instruments CDCVF25081 Product Info

1 April 2026 3

Parameters

Number of outputs

8

Additive RMS jitter (typ) (fs)

100

Core supply voltage (V)

3.3

Output supply voltage (V)

3.3

Output skew (ps)

150

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVTTL

Input type

LVTTL

Package

SOIC (D)-16-59.4 mm² 9.9 x 6

Features

  • Phase-locked loop based, zero-delay buffer
    • 1 clock input to 2 banks of 4 outputs
    • No external RC network required
  • Supply voltage: 3 V to 3.6 V
  • Operating frequency: 8 MHz to 200 MHz
  • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz
  • Power-down mode available
    • Current consumption: < 20 µA in

      Power-down mode

  • 25-Ω on-chip series damping resistors
  • Industrial temperature range: –40°C to 85°C
  • Spread Spectrum Clock Compatible (SSC)
  • Packaged in
    • 9.9-mm × 3.91-mm, 16-pin SOIC (D)
    • 5.0-mm × 4.4-mm, 16-pin TSSOP (PW)
  • Phase-locked loop based, zero-delay buffer
    • 1 clock input to 2 banks of 4 outputs
    • No external RC network required
  • Supply voltage: 3 V to 3.6 V
  • Operating frequency: 8 MHz to 200 MHz
  • Low additive jitter (cycle-cycle): ±100 ps for 66 MHz to 200 MHz
  • Power-down mode available
    • Current consumption: < 20 µA in

      Power-down mode

  • 25-Ω on-chip series damping resistors
  • Industrial temperature range: –40°C to 85°C
  • Spread Spectrum Clock Compatible (SSC)
  • Packaged in
    • 9.9-mm × 3.91-mm, 16-pin SOIC (D)
    • 5.0-mm × 4.4-mm, 16-pin TSSOP (PW)

Description

The CDCVF25081 is a high performance, low skew, low jitter, phased-locked loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The outputs are divided into 2 banks for a total of 8 buffered CLKIN outputs. The device automatically puts the outputs to a low state when no CLKIN signal is present (power down mode).

The S1 and S2 pins allow selection between PLL or bypassed PLL outputs. When left open, the outputs are disabled to a logic low state.

The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 3.3V supply environment and is characterized from –40°C to 85°C (ambient temperature).

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