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LMKDB1204
  • LMKDB1204
  • LMKDB1204

LMKDB1204

ACTIVE

2-input 4-output LP-HCSL clock multiplexer for PCIe Gen 1 to Gen 7

Texas Instruments LMKDB1204 Product Info

1 April 2026 0

Parameters

Number of outputs

4

Additive RMS jitter (typ) (fs)

19.2

Core supply voltage (V)

1.8, 3.3

Output supply voltage (V)

1.8, 3.3

Output skew (ps)

50

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LP-HCSL

Input type

LP-HCSL

Package

VQFN (REX)-28-16 mm² 4 x 4

Features

  • LP-HCSL clock MUX that support:
    • PCIe Gen 1 to Gen 7
    • CC (Common Clock) and IR (Independent Reference) PCIe architectures
    • Input clock with or without SSC
  • DB2000QL compliant:
    • All devices meet DB2000QL specifications
  • Extremely low additive jitter:
    • 31fs maximum 12kHz to 20MHz RMS additive jitter at 156.25MHz
    • 13fs maximum additive jitter for PCIe Gen 4
    • 5fs maximum additive jitter for PCIe Gen 5
    • 3fs maximum additive jitter for PCIe Gen 6
    • 2.1fs maximum additive jitter for PCIe Gen 7
  • Fail-safe input
  • Flexible power-up sequence
  • Automatic output disable
  • Individual output enable
  • SBI (Side Band Interface) for high-speed output enable or disable
  • LOS (Loss of Signal) input detection
  • 85Ω or 100Ω output impedance
  • 1.8V / 3.3V ± 10% power supply
  • –40°C to 105°C ambient temperature
  • LP-HCSL clock MUX that support:
    • PCIe Gen 1 to Gen 7
    • CC (Common Clock) and IR (Independent Reference) PCIe architectures
    • Input clock with or without SSC
  • DB2000QL compliant:
    • All devices meet DB2000QL specifications
  • Extremely low additive jitter:
    • 31fs maximum 12kHz to 20MHz RMS additive jitter at 156.25MHz
    • 13fs maximum additive jitter for PCIe Gen 4
    • 5fs maximum additive jitter for PCIe Gen 5
    • 3fs maximum additive jitter for PCIe Gen 6
    • 2.1fs maximum additive jitter for PCIe Gen 7
  • Fail-safe input
  • Flexible power-up sequence
  • Automatic output disable
  • Individual output enable
  • SBI (Side Band Interface) for high-speed output enable or disable
  • LOS (Loss of Signal) input detection
  • 85Ω or 100Ω output impedance
  • 1.8V / 3.3V ± 10% power supply
  • –40°C to 105°C ambient temperature

Description

The LMKDB devices are a family of extremely-low-jitter LP-HCSL clock muxes that support PCIe Gen 1 to Gen 7 and are DB2000QL compliant. The devices provide flexible power-up sequence, fail-safe inputs, individual output enable and disable pins, loss of input signal (LOS) detection and automatic output disable features, as well as excellent power supply noise rejection performance.

Both 1.8V and 3.3V power supply voltages are supported.

The LMKDB devices are a family of extremely-low-jitter LP-HCSL clock muxes that support PCIe Gen 1 to Gen 7 and are DB2000QL compliant. The devices provide flexible power-up sequence, fail-safe inputs, individual output enable and disable pins, loss of input signal (LOS) detection and automatic output disable features, as well as excellent power supply noise rejection performance.

Both 1.8V and 3.3V power supply voltages are supported.

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