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LMK5C33216
  • LMK5C33216

LMK5C33216

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Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW

Texas Instruments LMK5C33216 Product Info

1 April 2026 0

Parameters

Function

Clock network synchronizer

Number of outputs

16

Output type

CML, LVCMOS, LVDS, LVPECL

RMS jitter (fs)

50

Features

JESD204B

Output frequency (min) (MHz)

0.000000000001

Output frequency (max) (MHz)

3000

Input type

HCSL, LVCMOS, LVDS, LVPECL, XTAL

Supply voltage (min) (V)

3.135

Supply voltage (max) (V)

3.465

Operating temperature range (°C)

-40 to 85

Number of input channels

2

Package

VQFN (RGC)-64-81 mm² 9 x 9

Features

  • BAW APLL with 40 fs RMS jitter at 491.52 MHz
  • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs)
    • Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz
    • -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rate
  • Two differential or single-ended DPLL inputs
    • 1 Hz to 800 MHz differential
    • Hitless switching with phase cancellation and/or phase slew control
    • Priority based reference selection
  • 16 outputs with programmable format
    • 1000 MHz LVPECL/LVDS/HSDS
    • 3000 MHz CML on OUT4 and OUT6
    • 200 MHz LVCMOS on OUT0 and OUT1
  • Single 3.3-V supply with internal LDOs
  • I2C or 3-wire/4-wire SPI interface
  • Requires single XO/TCXO/OCXO
  • 40-bit DPLL or APLL DCO, < 1 ppt
  • Holdover with phase build out upon exit
  • Zero delay mode with programmable delay
  • User programmable EEPROM
  • Supports 105 °C PCB temperature
  • BAW APLL with 40 fs RMS jitter at 491.52 MHz
  • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs)
    • Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz
    • -116 dBc/Hz at 100 Hz offset at 122.88 MHz DPLL TDC noise with ≥ 20 MHz TDC rate
  • Two differential or single-ended DPLL inputs
    • 1 Hz to 800 MHz differential
    • Hitless switching with phase cancellation and/or phase slew control
    • Priority based reference selection
  • 16 outputs with programmable format
    • 1000 MHz LVPECL/LVDS/HSDS
    • 3000 MHz CML on OUT4 and OUT6
    • 200 MHz LVCMOS on OUT0 and OUT1
  • Single 3.3-V supply with internal LDOs
  • I2C or 3-wire/4-wire SPI interface
  • Requires single XO/TCXO/OCXO
  • 40-bit DPLL or APLL DCO, < 1 ppt
  • Holdover with phase build out upon exit
  • Zero delay mode with programmable delay
  • User programmable EEPROM
  • Supports 105 °C PCB temperature

Description

The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.

The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy.

The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains.

The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks.

The LMK5C33216 is a high-performance network clock generator, synchronizer, and jitter attenuator with advanced reference clock selection and hitless switching capabilities designed to meet the stringent requirements of communications infrastructure applications.

The LMK5C33216 integrates 3 DPLLs with programmable loop bandwidth and no external loop filters, maximizing flexibility and ease of use. Each DPLL phase locks a paired APLL to a DPLL reference input. The APLL reference determines the long term frequency accuracy.

The 3 APLLs may operate independent of their paired DPLL and be cascaded from another APLL to provide programmable frequency translation. APLL3 features ultra high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) VCBO technology and can generate output clocks with 40-fs RMS jitter independent of the jitter and frequency of the XO and reference inputs. APLL1 and APLL2 provide options for additional frequency domains.

The device is fully programmable through I2C or SPI interface. The onboard EEPROM can be used to customize system start-up clocks.

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