Product
0
LMK1D2102L
  • LMK1D2102L
  • LMK1D2102L
  • LMK1D2102L

LMK1D2102L

ACTIVE

Low additive jitter LVDS buffer

Texas Instruments LMK1D2102L Product Info

1 April 2026 1

Parameters

Number of outputs

2

Additive RMS jitter (typ) (fs)

5

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

Universal input

Package

VQFN (RGT)-16-9 mm² 3 x 3

Features

  • High-performance LVDS clock buffer family: up to 2GHz
    • Dual 1:2 differential buffer
    • Dual 1:4 differential buffer
    • Dual 1:6 differential buffer
    • Dual 1:8 differential buffer
  • Supply voltage: 1.71V to 3.465V
  • Dual output common mode voltage operation:
    • Output common mode voltage: 0.7V at 1.8V supply voltage.
    • Output common mode voltage: 1.2V at 2.5V/3.3V supply voltage
  • Low additive jitter:
    • < 17fs RMS typical in 12kHz to 20MHz at 1250.25MHz
    • < 22fs RMS typical in 12kHz to 20MHz at 625MHz
    • < 60fs RMS maximum in 12kHz to 20MHz at 156.25MHz
    • Very low phase noise floor: -164dBc/Hz (typical at 156.25MHz)
  • Very low propagation delay: < 575ps maximum
  • Output skew:
    • 15ps maximum (LMK1D2102, LMK1D2104)
    • 20ps maximum (LMK1D2106, LMK1D2106)
  • Part to Part skew: 150ps
  • High-swing LVDS (boosted mode): 500mV VOD typical when AMP_SELA, AMP_SELB= Floating
  • Bank enable/disable using AMP_SELA and AMP_SELB
  • Fail-safe input operation
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Extended industrial temperature range: –40°C to 105°C
  • High-performance LVDS clock buffer family: up to 2GHz
    • Dual 1:2 differential buffer
    • Dual 1:4 differential buffer
    • Dual 1:6 differential buffer
    • Dual 1:8 differential buffer
  • Supply voltage: 1.71V to 3.465V
  • Dual output common mode voltage operation:
    • Output common mode voltage: 0.7V at 1.8V supply voltage.
    • Output common mode voltage: 1.2V at 2.5V/3.3V supply voltage
  • Low additive jitter:
    • < 17fs RMS typical in 12kHz to 20MHz at 1250.25MHz
    • < 22fs RMS typical in 12kHz to 20MHz at 625MHz
    • < 60fs RMS maximum in 12kHz to 20MHz at 156.25MHz
    • Very low phase noise floor: -164dBc/Hz (typical at 156.25MHz)
  • Very low propagation delay: < 575ps maximum
  • Output skew:
    • 15ps maximum (LMK1D2102, LMK1D2104)
    • 20ps maximum (LMK1D2106, LMK1D2106)
  • Part to Part skew: 150ps
  • High-swing LVDS (boosted mode): 500mV VOD typical when AMP_SELA, AMP_SELB= Floating
  • Bank enable/disable using AMP_SELA and AMP_SELB
  • Fail-safe input operation
  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels
  • LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
  • Extended industrial temperature range: –40°C to 105°C

Description

The LMK1D210xL is a low noise dual clock buffer which distributes one input to a maximum of 2 (LMK1D2102L), 4 (LMK1D2104L), 6 (LMK1D2106L) or 8 (LMK1D2108L) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210xL is specifically designed for driving 50Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-8).

LMK1D210xL buffer offers two output common mode operation (0.7V and 1.2V) for different operating supply. The device provides flexibility in design for DC-coupled mode applications.

AMP_SELA / AMP_SELB control pin can be used to select different output amplitude LVDS (350mV) or boosted LVDS (500mV). In addition to amplitude selection, outputs can be disabled using the same pin.

The part also supports Fail-Safe Input function for clock and digital input pins. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The LMK1D210xL is a low noise dual clock buffer which distributes one input to a maximum of 2 (LMK1D2102L), 4 (LMK1D2104L), 6 (LMK1D2106L) or 8 (LMK1D2108L) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.

The LMK1D210xL is specifically designed for driving 50Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-8).

LMK1D210xL buffer offers two output common mode operation (0.7V and 1.2V) for different operating supply. The device provides flexibility in design for DC-coupled mode applications.

AMP_SELA / AMP_SELB control pin can be used to select different output amplitude LVDS (350mV) or boosted LVDS (500mV). In addition to amplitude selection, outputs can be disabled using the same pin.

The part also supports Fail-Safe Input function for clock and digital input pins. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Subscribe to Welllinkchips !
Your Name
* Email
Popular Posts
Featured Parts More >
Submit a request
CONTACT US
Company address

WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK

Send Enquiry
SEND e-MAIL
Office hour from 9am to 6pm ,
Monday through Friday, UTC/GMT +8