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SN54SC4T02-SEP
  • SN54SC4T02-SEP
  • SN54SC4T02-SEP

SN54SC4T02-SEP

ACTIVE

Radiation-tolerant, four-channel, two-input 1.2-V to 5.5-V NOR gate with integrated level shifter

Texas Instruments SN54SC4T02-SEP Product Info

1 April 2026 1

Parameters

Technology family

SCxT

Number of channels

4

Vout (min) (V)

1.2

Vout (max) (V)

5.5

Features

Balanced outputs, Over-voltage tolerant inputs, Voltage translation

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Operating temperature range (°C)

-55 to 125

Package

TSSOP (PW)-14-32 mm² 5 x 6.4

Features

  • Vendor item drawing available, VID V62/23628-01XE
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2 V to 5.5 V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2 V V CC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2 V
        • 2.5-V – Inputs from 1.8 V
        • 3.3-V – Inputs from 1.8 V, 2.5 V
        • 5.0-V – Inputs from 2.5 V, 3.3 V
      • Down translation:

        • 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V, 5.0 V

        • 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
        • 2.5-V – Inputs from 3.3 V, 5.0 V
        • 3.3-V – Inputs from 5.0 V
  • 5.5 V tolerant input pins
  • Output drive up to 25 mA AT 5-V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification
  • Vendor item drawing available, VID V62/23628-01XE
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2 V to 5.5 V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2 V V CC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2 V
        • 2.5-V – Inputs from 1.8 V
        • 3.3-V – Inputs from 1.8 V, 2.5 V
        • 5.0-V – Inputs from 2.5 V, 3.3 V
      • Down translation:

        • 1.2-V – Inputs from 1.8 V, 2.5 V, 3.3 V, 5.0 V

        • 1.8-V – Inputs from 2.5 V, 3.3 V, 5.0 V
        • 2.5-V – Inputs from 3.3 V, 5.0 V
        • 3.3-V – Inputs from 5.0 V
  • 5.5 V tolerant input pins
  • Output drive up to 25 mA AT 5-V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification

Description

The SN54SC4T02-SEP contains four independent 2-input NOR Gates with extended voltage operation to allow for level translation. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.2-V, 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output).

The SN54SC4T02-SEP contains four independent 2-input NOR Gates with extended voltage operation to allow for level translation. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.2-V, 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output).

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