0
ACTIVE
Number of outputs |
4 |
Additive RMS jitter (typ) (fs) |
50 |
Core supply voltage (V) |
1.8, 2.5, 3.3 |
Output supply voltage (V) |
1.8, 2.5, 3.3 |
Output skew (ps) |
20 |
Operating temperature range (°C) |
-40 to 105 |
Rating |
Catalog |
Output type |
LVDS |
Input type |
HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL |
VQFN (RHD)-28-25 mm² 5 x 5
Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
The LMK1D1204P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.
The LMK1D1204P is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high "1". If this pin is set to a logic low "0", the output is disabled in a high Z state resulting in reduced power consumption.
The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
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