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DLPC3420
  • DLPC3420
  • DLPC3420
  • DLPC3420

DLPC3420

ACTIVE

DLP® display controller for DLP160AP (0.16 QnHD) DMD

Texas Instruments DLPC3420 Product Info

1 April 2026 3

Parameters

Component type

Display Controller

Chipset family

DLP160AP, DLPA2000, DLPA2005, DLPC3420

Display resolution (max)

QnHD (320x180)

Operating temperature range (°C)

0 to 70

Rating

Catalog

Package

NFBGA (ZVB)-176-49 mm² 7 x 7

Features

  • Display controller for DLP160AP (0.16 QnHD) DMD
    • Supports input resolutions up to QnHD
    • Low-power DMD interface with interface training
  • Input frame rates up to 60 Hz
  • Pixel data processing:
    • Content adaptive illumination control (CAIC)
    • 1D Keystone correction
    • Color coordinate adjustment
    • Active power management processing
    • Programmable degamma
    • Color space conversion
    • 4:2:2 to 4:4:4 chroma interpolation
  • 24-bit, input pixel interface support:
    • Parallel or BT656, interface protocols
    • Pixel clock up to 155 MHz
    • Multiple input pixel data format options
  • MIPI DSI (display serial interface) type 3:
    • 1-4 lanes, up to 470-Mbps lane speed
  • External flash support
  • Auto DMD parking at power down
  • Embedded frame memory (eDRAM)
  • System features:
    • I2C device control
    • Programmable splash screens
    • Programmable LED current control
    • Display image rotation
  • Pair with DLPA2000 and DLPA2005 PMIC (power management integrated circuit) and LED driver
  • Display controller for DLP160AP (0.16 QnHD) DMD
    • Supports input resolutions up to QnHD
    • Low-power DMD interface with interface training
  • Input frame rates up to 60 Hz
  • Pixel data processing:
    • Content adaptive illumination control (CAIC)
    • 1D Keystone correction
    • Color coordinate adjustment
    • Active power management processing
    • Programmable degamma
    • Color space conversion
    • 4:2:2 to 4:4:4 chroma interpolation
  • 24-bit, input pixel interface support:
    • Parallel or BT656, interface protocols
    • Pixel clock up to 155 MHz
    • Multiple input pixel data format options
  • MIPI DSI (display serial interface) type 3:
    • 1-4 lanes, up to 470-Mbps lane speed
  • External flash support
  • Auto DMD parking at power down
  • Embedded frame memory (eDRAM)
  • System features:
    • I2C device control
    • Programmable splash screens
    • Programmable LED current control
    • Display image rotation
  • Pair with DLPA2000 and DLPA2005 PMIC (power management integrated circuit) and LED driver

Description

The DLPC3420 digital controller, part of the DLP160AP (0.16 QnHD) chipset, enables operation of the DLP160AP digital micromirror device (DMD). The DLPC3420 controller provides a convenient, multi-functional interface between user electronics and the DMD, enabling small form factor and low power display applications.

Visit the getting started with TI DLP Pico™ display technology page, and view the programmer’s guide to learn how to get started.

The chipset includes established resources to help the user accelerate the design cycle, which includeproduction ready optical modules, optical module manufacturers, and design houses.

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