0
ACTIVE
Sample rate (max) (Msps) |
250 |
Resolution (Bits) |
14 |
Number of input channels |
2 |
Interface type |
DDR LVDS |
Analog input BW (MHz) |
1400 |
Features |
Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power |
Rating |
Catalog |
Peak-to-peak input voltage range (V) |
2 |
Power consumption (typ) (mW) |
470 |
Architecture |
Pipeline |
SNR (dB) |
74 |
ENOB (Bits) |
12 |
SFDR (dB) |
83 |
Operating temperature range (°C) |
-40 to 85 |
Input buffer |
Yes |
VQFNP (RTD)-64-81 mm² 9 x 9
The ADC3648 and ADC3649 (ADC364x) are a 14-bit, 250MSPS and 500MSPS, dual channel analog to digital converter (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -158.5dBFS/Hz (500MSPS).
The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).
The ADC364x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.
The ADC364x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 14-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation rates, the output resolution can be increased to 32-bit.
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