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ADC3222
  • ADC3222
  • ADC3222
  • ADC3222
  • ADC3222

ADC3222

ACTIVE

Dual-Channel, 12-Bit, 50-MSPS Analog-to-Digital Converter (ADC)

Texas Instruments ADC3222 Product Info

1 April 2026 4

Parameters

Sample rate (max) (Msps)

50

Resolution (Bits)

12

Number of input channels

2

Interface type

Serial LVDS

Analog input BW (MHz)

540

Features

Low Power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

148

Architecture

Pipeline

SNR (dB)

71.1

ENOB (Bits)

11.5

SFDR (dB)

95

Operating temperature range (°C)

-40 to 85

Input buffer

No

Package

VQFN (RGZ)-48-49 mm² 7 x 7

Features

  • Dual channel
  • 12-Bit resolution
  • Single supply: 1.8 V
  • Serial LVDS interface (SLVDS)
  • Flexible input clock buffer with divide-by-1, -2, -4
  • SNR = 70.2 dBFS, SFDR = 87 dBc at fIN = 70 MHz
  • Ultra-low power consumption:
    • 116 mW/Ch at 125 MSPS
  • Channel isolation: 105 dB
  • Internal dither and chopper
  • Support for multi-chip synchronization
  • Pin-to-pin compatible with 14-Bit version
  • Package: VQFN-48 (7 mm × 7 mm)
  • Dual channel
  • 12-Bit resolution
  • Single supply: 1.8 V
  • Serial LVDS interface (SLVDS)
  • Flexible input clock buffer with divide-by-1, -2, -4
  • SNR = 70.2 dBFS, SFDR = 87 dBc at fIN = 70 MHz
  • Ultra-low power consumption:
    • 116 mW/Ch at 125 MSPS
  • Channel isolation: 105 dB
  • Internal dither and chopper
  • Support for multi-chip synchronization
  • Pin-to-pin compatible with 14-Bit version
  • Package: VQFN-48 (7 mm × 7 mm)

Description

The ADC322x are a high-linearity, ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC322x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.

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