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ADC12QJ1600-SP
  • ADC12QJ1600-SP
  • ADC12QJ1600-SP
  • ADC12QJ1600-SP

ADC12QJ1600-SP

ACTIVE

Radiation-hardness-assured (RHA), 300-krad, 12-bit, quad-channel, 1.6-GSPS ADC

Texas Instruments ADC12QJ1600-SP Product Info

1 April 2026 0

Parameters

Sample rate (max) (Msps)

1600

Resolution (Bits)

12

Number of input channels

4

Interface type

JESD204B, JESD204C

Analog input BW (MHz)

6000

Features

Ultra High Speed

Rating

Space

Peak-to-peak input voltage range (V)

0.8

Power consumption (typ) (mW)

1910

Architecture

Folding Interpolating

SNR (dB)

57.4

ENOB (Bits)

9

SFDR (dB)

64

Operating temperature range (°C)

-55 to 125

Input buffer

Yes

Radiation, TID (typ) (krad)

300

Radiation, SEL (MeV·cm2/mg)

120

Package

FCCSP (ALR)-144-100 mm² 10 x 10

Features

  • Radiation Performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100 MHz): 57.4dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64dBc
    • Noise floor (–20dBFS): –147dBFS
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS): 1.9W
  • Power supplies: 1.1V, 1.9V
  • Radiation Performance:
    • Total Ionizing Dose (TID): 300 krad (Si)
    • Single Event Latchup (SEL): 120 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100 MHz): 57.4dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64dBc
    • Noise floor (–20dBFS): –147dBFS
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS): 1.9W
  • Power supplies: 1.1V, 1.9V

Description

ADC12QJ1600-SP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of multi-channel communications systems.

Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC12QJ1600-SP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of multi-channel communications systems.

Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

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