0
ADC12DJ1600-Q1
  • ADC12DJ1600-Q1
  • ADC12DJ1600-Q1
  • ADC12DJ1600-Q1
  • ADC12DJ1600-Q1

ADC12DJ1600-Q1

ACTIVE

Automotive, 2-ch, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator

Texas Instruments ADC12DJ1600-Q1 Product Info

1 April 2026 0

Parameters

Sample rate (max) (Msps)

1600

Resolution (Bits)

12

Number of input channels

2

Interface type

JESD204B, JESD204C

Analog input BW (MHz)

6000

Features

Ultra High Speed

Rating

Automotive

Peak-to-peak input voltage range (V)

0.8

Power consumption (typ) (mW)

1760

Architecture

Folding Interpolating

SNR (dB)

57

ENOB (Bits)

9.1

SFDR (dB)

67

Operating temperature range (°C)

-40 to 125

Input buffer

Yes

Package

FCCSP (AAV)-144-100 mm² 10 x 10

Features

  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100MHz): 57.4dBFS
    • ENOB (100MHz): 9.1 Bits
    • SFDR (100MHz): 64dBc
    • Noise floor (–20dBFS): –147dBFS
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS):
    • Quad Channel: 477mW / channel
    • Dual channel: 700mW / channel
    • Single channel: 1000mW
  • Power supplies: 1.1V, 1.9V
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100MHz): 57.4dBFS
    • ENOB (100MHz): 9.1 Bits
    • SFDR (100MHz): 64dBc
    • Noise floor (–20dBFS): –147dBFS
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS):
    • Quad Channel: 477mW / channel
    • Dual channel: 700mW / channel
    • Single channel: 1000mW
  • Power supplies: 1.1V, 1.9V

Description

ADC12xJ1600-Q1 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600-Q1 suited for light detection and ranging (LiDAR) systems. ADC12xJ1600-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC12xJ1600-Q1 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600-Q1 suited for light detection and ranging (LiDAR) systems. ADC12xJ1600-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

Subscribe to Welllinkchips !
Your Name
* Email
Submit a request