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S80KS5123GABHB020
  • S80KS5123GABHB020

S80KS5123GABHB020

Active and preferred

The S80KS5123GABHB020 is a 512 Mb HYPERRAM™ self-refresh DRAM with 1.8 V array and I/O and an octal xSPI slave interface. It uses an 8-bit DDR data bus with 16-bit word address boundaries, supporting up to 200 MHz clock and 400 MBps throughput with tACC 35 ns. RWDS indicates refresh latency and acts as read strobe or write mask. It supports hybrid sleep and 30 µA deep power down at 105°C, and is AEC-Q100 Grade 2 qualified for -40 to 105°C.

Infineon Technologies S80KS5123GABHB020 Product Info

16 April 2026 1

Parameters

Density

512 MBit

Family

KS-3

Initial Access Time

35 ns

Interface Bandwidth

400 MByte/s

Interface Frequency (SDR/DDR) (MHz)

- / 200

Interfaces

xSPI (Octal)

Lead Ball Finish

Sn/Ag/Cu

Operating Temperature range

-40 °C to 105 °C

Operating Voltage range

1.7 V to 2 V

Operating Voltage

1.8 V

Peak Reflow Temp

260 °C

Planned to be available until at least

See roadmap

Qualification

Automotive

Technology

HYPERRAM

Features

  • Octal xSPI interface with CS#
  • 8-bit DQ[7:0] data bus
  • DDR data on both clock edges
  • 200 MHz maximum clock rate
  • Up to 400 MBps data throughput
  • 35 ns maximum access time (tACC)
  • RWDS strobe, mask, latency flag
  • Configurable bursts: linear or wrap
  • Wrap bursts: 16/32/64/128 bytes
  • Hybrid sleep via CR1[5], retains data
  • Deep power down via CR0[15]
  • VCC supply range 1.7 V to 2.0 V

Description

  • Connects to xSPI host controllers
  • High bandwidth for code/data fetch
  • DDR boosts throughput per clock
  • 200 MHz supports fast memory access
  • 35 ns tACC cuts read latency
  • RWDS eases timing margin closure
  • Burst modes match cache-line reads
  • Wrapped bursts reduce bus overhead
  • Hybrid sleep saves power, keeps data
  • Deep power down minimizes leakage
  • Active clock stop saves stalled power
  • 1.8 V rails without extra supplies

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