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S70KL1282DPBHI020
  • S70KL1282DPBHI020

S70KL1282DPBHI020

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S70KL1282DPBHI020 is a 128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) with a HYPERBUS™ interface, 8-bit DDR data bus, and RWDS strobe (data strobe or write mask). It is a 3.0 V-only device operating at 2.7 V to 3.60 V, supports DP speed up to 166 MHz, and specifies 35 ns max access time. Configurable linear or wrapped bursts and standby, hybrid sleep, and deep power down modes are supported in a 24-ball FBGA.

Infineon Technologies S70KL1282DPBHI020 Product Info

16 April 2026 0

Parameters

Density

128 MBit

Family

KL-2

Initial Access Time

36 ns

Interface Bandwidth

333 MByte/s

Interface Frequency (SDR/DDR) (MHz)

- / 166

Interfaces

HYPERBUS

Lead Ball Finish

N/A

Operating Temperature range

-40 °C to 85 °C

Operating Voltage range

2.7 V to 3.6 V

Operating Voltage

3 V

Peak Reflow Temp

260 °C

Planned to be available until at least

See roadmap

Qualification

Industrial

Technology

HYPERRAM

Apps

Programmable logic controller (PLC)

Features

  • HYPERBUS interface
  • 1.7 V to 2.0 V VCC option
  • 2.7 V to 3.60 V VCC option
  • 8-bit DDR data bus (DQ[7:0])
  • 200 MHz maximum clock rate
  • Up to 400 MBps throughput
  • 35 ns maximum access time (tACC)
  • Wrapped bursts 16/32/64/128 B
  • RWDS strobe and write data mask
  • DCARS option shifts RWDS phase
  • Hybrid sleep retains data
  • Deep power down stops refresh

Description

  • High bandwidth with few pins
  • Fits 1.8 V or 3.0 V logic rails
  • DDR bus reduces system pin count
  • 200 MHz supports fast processors
  • 400 MBps feeds high-rate buffers
  • 35 ns tACC reduces read latency
  • Burst sizes match cache-line needs
  • RWDS eases DDR timing closure
  • DCARS improves read eye margin
  • Hybrid sleep cuts power, keeps data
  • DPD minimizes leakage when off
  • Clock-stop lowers stall current

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