0
Active and preferred
Architecture |
NoBL, Flow-through |
Bank Switching |
N |
Burst Length (Words) |
4 |
Data Width |
x 36 |
Density |
18 MBit |
ECC |
Y |
Family |
Synchronous SRAM with ECC |
Frequency |
100 MHz |
Interfaces |
Parallel |
Lead Ball Finish |
Pure Sn |
On-Die Termination |
N |
Operating Temperature range |
-40 °C to 85 °C |
Operating Voltage range |
3.135 V to 3.6 V |
Organization (X x Y) |
512Kb x 36 |
Peak Reflow Temp |
260 °C |
Planned to be available until at least |
2031 |
Qualification |
Industrial |
Read Latency (Cycles) |
1 |
WELL LINK CHIPS GROUP CO.,LIMITED FLAT/RM 1802 BEVERLY HOUSE 93-107 LOCKHART ROAD WANCHAI HK
