The STM32H573VIT6 sits at a compelling intersection within ST’s STM32H5 portfolio: it delivers the full 250 MHz Cortex-M33 computational engine and the enhanced hardware cryptography block of the H573 line, while adopting the widely used LQFP100 package that fits comfortably into mainstream PCB designs. For engineering teams that need robust security without committing to the highest pin-count packages, this device offers a pragmatic balance between capability, board space, and design familiarity.

At the heart of the STM32H573VIT6 is an Arm Cortex-M33 core running at up to 250 MHz, achieving 375 DMIPS (Dhrystone 2.1) and a CoreMark score of 1023 (4.092 CoreMark/MHz). The core integrates a single-precision floating-point unit (FPU) and a memory protection unit (MPU), making it suitable for control algorithms that involve floating-point arithmetic without resorting to software emulation.

The memory subsystem is designed for deterministic execution. The device carries 2 MB of embedded flash with ECC, organized in two banks that support read-while-write operation—a useful property when firmware updates must proceed while the application continues running from the other bank. The 640 KB SRAM is partitioned into 64 KB SRAM2 with ECC, 320 KB SRAM3 with flexible ECC, and 4 KB backup SRAM retained in the lowest power modes. An ART Accelerator with 8 KB instruction cache and 4 KB data cache enables zero-wait-state execution from flash and external memories, reducing the performance penalty that often accompanies large code footprints.

The LQFP100 package exposes 80 I/O pins, most of which are 5 V tolerant—a practical advantage in industrial environments where legacy 5 V peripherals remain common. The 16-channel 12-bit ADC configuration is sufficient for multi-sensor acquisition without external multiplexing in many monitoring and control applications.

What distinguishes the H573 line from the H563 within the STM32H5 family is the presence of a dedicated hardware cryptography engine on top of TrustZone. The STM32H573VIT6 includes AES symmetric acceleration, a PKA public-key accelerator supporting RSA and ECC, and OTFDEC for on-the-fly decryption of external flash content. These blocks execute cryptographic operations in hardware rather than consuming CPU cycles, which matters for applications that maintain TLS/SSL sessions, perform secure boot verification, or encrypt data at rest.

Beyond the accelerators, the device integrates ST-iROT, a preconfigured immutable root of trust, and supports secure firmware installation and secure debugging mechanisms. TrustZone itself provides hardware-enforced isolation between secure and non-secure domains, with up to eight configurable SAU regions for runtime memory partitioning. This architecture allows a secure processing environment for key management and authentication to coexist with a rich non-secure application domain running middleware, communication stacks, and user interface code.

The peripheral set of the STM32H573VIT6 is oriented toward connected industrial and consumer equipment. The device provides dual FDCAN controllers, Ethernet MAC support, USB Full-Speed and High-Speed OTG, and a broad array of serial interfaces including SPI, I²C, I3C, USART, UART, LPUART, and SAI. For memory expansion, the flexible memory controller supports SRAM, PSRAM, SDRAM/LPSDR SDRAM, FRAM, and NOR/NAND devices, while an Octo-SPI interface accommodates serial PSRAM, NAND, NOR, and HyperRAM/HyperFlash formats.

A summary of the key configuration parameters is shown below.

The timer complement includes two 32-bit general-purpose timers, two advanced-control 16-bit timers for motor control, multiple 16-bit general-purpose and basic timers, and six low-power 16-bit timers, giving control-oriented designs enough PWM and capture resources without external timer ICs.

The STM32H573VIT6 is appropriate when three conditions converge: the application needs the full H573 security feature set (hardware crypto plus TrustZone plus ST-iROT), the board can accommodate a 100-pin LQFP but does not require the very high I/O density of a 144-pin device, and the operating temperature ceiling of 85 °C aligns with the thermal profile. In the H573 line, the VIT6 offers the security engine without the additional cost and board complexity of the larger LQFP144 variant. Compared with H563-class devices, the VIT6 is the choice when cryptographic workloads must be offloaded from the CPU or when a hardware root of trust is a system requirement rather than an optional hardening step.

The combination of hardware crypto, TrustZone, and a moderate pin count positions the STM32H573VIT6 for secure IoT gateways, industrial communication nodes that require authenticated firmware updates, access-control terminals, and medical monitoring devices where data integrity and device identity are consequential. In these systems, the non-secure domain can run the network stack and application logic, while the secure domain handles key storage, session establishment, and image verification. The dual-bank flash supports fail-safe over-the-air update schemes, and the read-while-write capability allows the new image to be programmed while the current application continues executing.

Development on the STM32H573VIT6 follows the STM32CubeH5 ecosystem. STM32CubeMX provides a graphical interface for pin assignment, clock tree configuration, and—critically for this device—TrustZone resource partitioning. When TrustZone is enabled, the tool generates separate secure and non-secure projects, and the build sequence requires compiling the secure project before the non-secure application. The STM32CubeH5 package includes HAL and LL drivers, middleware for USB, TCP/IP, file systems, RTOS, and graphics, and examples that run on the STM32H573I-DK Discovery board, which features the same silicon family and serves as a functional reference platform for early evaluation.

For security development, ST provides STM32TrustedPackageCreator and the ST-iROT boot path configuration tools. STM32CubeProgrammer supports provisioning of the secure boot path and option bytes. Teams that adopt the Secure Manager framework can leverage STM32TRUSTEE-SM for PSA-certified security services, although this requires careful configuration of the boot path and memory partitioning from the outset of the project.

The STM32H573VIT6 is best understood as the “accessible secure” member of the H573 family. It preserves the 250 MHz performance envelope, the dual-bank 2 MB flash architecture, and the full hardware cryptography subsystem, while packaging them in a 100-pin footprint that is familiar to a broad range of embedded designers. It is not the smallest or the most pin-rich option in the STM32H5 lineup, but for applications where security is a design requirement rather than an afterthought—and where board space and cost remain practical constraints—it offers a well-proportioned engineering solution.