The STM32H563VGT6 occupies a pragmatic middle ground in the STM32H5 lineup. It retains the Ethernet MAC, dual FDCAN controllers, and TrustZone security foundation of the H563 class, while compressing them into a 100-pin LQFP package with 80 I/O pins. For engineering teams that need a networked, protected microcontroller but do not require the 112-pin interface density of a 144-pin device, this configuration offers a direct route to board designs that are simpler to route, less expensive to assemble, and compatible with the extensive ecosystem of 100-pin STM32 footprints.

The LQFP100 package of the STM32H563VGT6 measures 14 × 14 mm and exposes 80 general-purpose I/Os, most of which are 5 V tolerant. This pin count is sufficient for a networked industrial node—Ethernet RMII or MII, CAN FD, a USB port, several serial buses, and a practical number of analog and digital I/O—without the routing congestion that can accompany a 144-pin device on a compact PCB.

The analog subsystem provides two 12-bit ADCs with 16 external channels and a two-channel 12-bit DAC. The 16-channel allocation reflects the reduced pin budget: it supports a credible multi-sensor front end for monitoring and control, but it does not offer the per-sensor dedicated channel count of the 144-pin variant. Designs with a larger analog sensor array must either multiplex channels externally or select the higher-pin-count option.

A compact parameter table provides the essential configuration.

The Cortex-M33 core runs at 250 MHz with 375 DMIPS and 1023 CoreMark, supported by an 8 KB instruction cache and 4 KB data cache for zero-wait-state execution from flash and external memories. The 1 MB embedded flash is organized in two banks with ECC and read-while-write capability, and each bank includes up to 48 KB of high-cycling data flash for frequently updated parameters. The 640 KB SRAM follows the same partitioning as the wider H563 devices: 64 KB of SRAM2 with full ECC, 320 KB of SRAM3 with flexible ECC, and 4 KB of backup SRAM retained in the lowest power modes.

The 1 MB flash capacity is the principal memory trade-off of the VGT6 relative to 2 MB members of the H563 family. For applications whose secure and non-secure images, middleware, and data-logging buffers fit within 1 MB, the device offers a lower-cost entry point to the H563 feature set. Applications with larger code images—particularly those running graphical stacks, full protocol suites, or extensive application code alongside a secure partition—should evaluate their flash budget carefully, because the dual-bank read-while-write architecture requires that the inactive bank be large enough to hold the update image during an over-the-air programming cycle.

TrustZone with the Armv8-M mainline extension, eight SAU regions, a HASH accelerator, ECDSA signature verification, a NIST SP800-90B TRNG, and active tamper detection constitute the security toolkit of the STM32H563VGT6. Secure firmware installation and TF-M-based secure upgrade are supported, and the device life cycle can be managed with authenticated debug control.

As with all H563 devices, dedicated AES and public-key accelerators are absent. Symmetric encryption and ECDSA signing operations execute on the Cortex-M33 core, with the HASH engine available for digest calculations. This is a deliberate architecture: the H563 class preserves TrustZone isolation and hardware-assisted integrity functions while leaving bulk cryptographic acceleration to the H573 tier. The practical consequence is that security workloads must be budgeted against CPU cycles, particularly during boot-time verification and secure session establishment. For a networked device that establishes TLS sessions at moderate frequency or verifies firmware at boot and at update boundaries, the 250 MHz core provides sufficient headroom in most cases. Continuous high-rate cryptographic processing is better served by a device with dedicated accelerators.

The Ethernet MAC supports 10/100 Mbps operation with DMA and IEEE 1588 time-stamping, making the VGT6 suitable for industrial Ethernet nodes and gateways that require time synchronization. Two FDCAN controllers provide fieldbus connectivity with CAN FD frame support, and the combination of Ethernet and dual CAN on a single 100-pin device is a distinguishing feature for protocol-bridging applications.

The serial interface set includes up to four I²C FM+ ports, one I3C, up to twelve USART/UART/LPUART instances, and five SPI interfaces (with additional SPI-capable USARTs in synchronous mode). USB 2.0 full-speed host/device is available for device connectivity and firmware update paths, and a USB Type-C/USB Power Delivery controller extends the interface capability to power-negotiation applications. The timer architecture includes two 32-bit timers, ten 16-bit general-purpose timers, two advanced-control timers for motor control, and six low-power timers operable in Stop mode. CORDIC and FMAC accelerators offload trigonometric and filtering computations.

The STM32H563VGT6 is the appropriate selection when the system requires Ethernet and CAN FD connectivity, TrustZone-based domain separation, and 250 MHz Cortex-M33 performance, and when the board can be realized within 80 I/O pins and a 1 MB flash budget. It is a natural fit for the 100-pin class of industrial controllers that must add network connectivity without a board respin to a larger package.

The primary alternatives within the same family clarify the decision boundaries. The STM32H563ZGT6 adds 32 I/O, four additional ADC channels, and the same 1 MB flash in a 144-pin package for designs that have exhausted the 100-pin budget. The STM32H562VIT6 retains the 100-pin/80 I/O envelope and doubles the flash to 2 MB but removes the Ethernet MAC and one FDCAN controller—a trade that favors code-heavy, connectivity-light applications over networked ones. The H573 devices add hardware AES and public-key acceleration at the cost of a different cost and package profile. The VGT6’s position is therefore defined by the simultaneous presence of Ethernet, dual CAN, and TrustZone in a mainstream 100-pin footprint with a 1 MB flash allocation.

Industrial communication nodes that bridge Ethernet and CAN FD segments are a primary application, particularly where authenticated remote firmware update and secure key storage are required. Motor-control platforms with a single or dual-axis scope can use the advanced-control timers and 16 ADC channels for current and position feedback while the Ethernet MAC provides connectivity to a supervisory controller. Building automation and access-control equipment benefit from the TrustZone secure partition for credential storage and the non-secure domain for protocol stacks and user-interface logic. Medical monitoring devices with a moderate analog channel count and a need for device authentication and secure data transport also align with the VGT6 configuration.

STM32CubeMX provides pin-validated configuration for the LQFP100 package and generates separate secure and non-secure projects when TrustZone is enabled. The STM32CubeH5 package supplies HAL/LL drivers, middleware, and examples for the H563 class, including Ethernet, USB, and TrustZone partitioning demonstrations. The NUCLEO-H563ZI board is based on the 2 MB H563ZI in a 144-pin package, but its Ethernet PHY interface, USB circuitry, and TrustZone examples are functionally representative of the VGT6’s peripherals; pin mapping differences are resolved in CubeMX before layout. For secure provisioning, the OEMiRoT flow for STM32H563 devices and the STM32TrustedPackageCreator toolchain provide a documented path from development to production.

The STM32H563VGT6 is a connectivity-first microcontroller that does not demand a connectivity-first board footprint. It delivers Ethernet, dual CAN FD, TrustZone, and 250 MHz Cortex-M33 computing within a 100-pin LQFP and a 1 MB dual-bank flash architecture, accepting the interface and memory trade-offs that this envelope implies. For embedded systems in which network presence and hardware-enforced isolation matter more than maximum pin count or cryptographic acceleration, the VGT6 represents a deliberately balanced configuration—one that prioritizes integration efficiency over raw expansion capacity.